Sharp DV-760H (serv.man3) Service Manual ▷ View online
DV-700S
DV-760S/H
DV-760S/H
11-9. IC507 BR93L46F
EEPROM
Terminal
Terminal name
In/Output
Function
2
VCC
–
Power
7
GND
–
All input/output reference voltage, 0V
3
CS
Input
Tip select input
4
CLK
Input
Sirial clock input
5
DIN
Input
Start bit, operation code, address and serial data input
6
OCNT
Output
Serial data output, READY/BUSY internal status indication output
• Block Diagram
C S
S K
D I
D O
Dummy bit
Instruction
register
register
Data
resistor
resistor
R/W
Amp.
Address
buffer
buffer
Address
Decoder
Decoder
Instruction decode control
clock generation
Wave voltage
detection
detection
Write
inhibition
inhibition
High voltage
generation
generation
bit
EEPROM
Aray
1,024
6bit
6bit
16bit
16bit
1
VDD
–
Digitan power +3.3V
2
HADR (0)
Input
CPU Address bus
3
HADR (1)
Input
CPU Address bus
4
HADR (2)
Input
CPU Address bus
5
HADR (3)
Input
CPU Address bus
6
HADR (4)
Input
CPU Address bus
7
HADR (5)
Input
CPU Address bus
8
VSS
–
Digital GND
9
VDD
–
Digitan power +3.3V
10
HADR (6)
Input
CPU Address bus
11
HADR (7)
Input
CPU Address bus
12
HADAT (0)
Input
CPU Data bus
13
HADAT (1)
Input
CPU Data bus
14
HADAT (2)
Input
CPU Data bus
15
HADAT (3)
Input
CPU Data bus
16
VSS
–
Digital GND
17
VDD
–
Digitan power +3.3V
18
HADAT (4)
Input
CPU Data bus
19
HADAT (5)
Input
CPU Data bus
20
HADAT (6)
Input
CPU Data bus
21
HADAT (7)
Input
CPU Data bus
22
INT
Input
CPU Data bus
23
WAIT
Input
CPU Data bus
24
VSS
–
Digital GND
25
VDD
–
Digitan power +3.3V
26
HRD
Input
CPU read signal
27
HWR
Input
CPU write signal
28
HAS
Input
CPU address strobe signal
29
HCS
Input
CPU tip select signal
30
HIM
Input
CPU bus control selection signal (I/M mode = H/L)
11-10. IC508 IX1516GE
GAMMA S-P-TONE
Terminal
Terminal name
In/Output
Function
11-9
DV-700S
DV-760S/H
DV-760S/H
31
MRST
Input
Reset signal
32
VSS
–
Digital GND
33
VDD
–
Digital power +3.3V
34
PXDO (0)
Output
Pixel data output
35
PXDO (1)
Output
8-bit parallel video data conforming to ITU-R BT.601 and BT.656 standard (Cb/Y/Cr/Y)
36
PXDO (2)
Output
MSB=PXDO(7), LSB=PXDO(0)
37
PXDO (3)
Output
38
PXDO (4)
Output
39
PXDO (5)
Output
40
VSS
–
Digital GND
41
VDD
–
Digital power +3.3V
42
PXDO (6)
Output
43
PXDO (7)
Output
44
PXCLKO
Output
Reference clock output for pixel data. 27 MHz
45
VSYNCO
Output
Vertical sync signal output
46
HSYNCO
Output
Horizontal sync signal output
47
VSYNCI
Input
Vertical sync signal output
48
VSS
–
Digital GND
49
VDD
–
Digital power +3.3V
50
HSYNCI
Input
Horizontal sync signal output
51
PXCLKI
Input
Reference clock output for pixel data. 27 MHz
52
PXDI (0)
Input
Pixel data output
53
PXDI (1)
Input
8-bit parallel video data conforming to ITU-R BT.601 and BT.656 standard (Cb/Y/Cr/Y)
54
PXDI (2)
Input
MSB=PXDI(7), LSB=PXDI(0)
55
PXDI (3)
Input
56
VSS
–
Digital GND
57
VDD
–
Digital power +3.3V
58
PXDI (4)
Input
59
PXDI (5)
Input
60
PXDI (6)
Input
61
PXDI (7)
Input
62
TEST0
Input
Test terminal
63
TEST1
Input
Test terminal
64
VSS
–
Digital GND
Terminal
Terminal name
In/Output
Function
• Block Diagram
12
HADAT
PXDI
HSYNCI
HADR
HCS HAS HWR HRD
HIM MRST
VDD
VSS
TEST0
TEST1
INT
WAIT
PXDO
VSYNCO
HSYNCO
PXCLKI
VSYNCI
PXCLKO
64pin LQFP
18
8
8
8
1
1
1
1
1
1
1
1
15
10 11
2
7
21
29
28
27
26
30
31
1 9
8
17
16
25
24 32
33 41
40 48
49 57
56 64
62
63
22
23
39
34
43
45
46
42
44
51
47
50
55 61
52 58
CPU
Host interface
ITU-R
601/656
interface
601/656
interface
ITU-R
601/656
formatter
601/656
formatter
Timing
generation
generation
Clock
Gen.
Gen.
Source
Dec.
Dec.
NTSC Enc.
(3ch D/A built in)
Edge
creation
SPT circuit
creation
SPT circuit
Digital
dinamic
r circuit
dinamic
r circuit
Digital color correction
Color
offset
correction
offset
correction
White
correction
correction
DR-SPT
circuit
circuit
8
1
1
1
1
11-10
DV-700S
DV-760S/H
DV-760S/H
11-11. IC512 IX1535GE
HOST I/F
1
VDD
–
Power +3.3V
2
HADR0
Input
CPU Address bus
3
HADR1
Input
CPU Address bus
4
HADR2
Input
CPU Address bus
5
HCS
Input
CPU Tip select
6
HWR
Input
CPU Write signal
7
HRD
Input
CPU Read signal
8
HDAT0
In/Output
CPU Data bus
9
HDAT1
In/Output
CPU Data bus
10
HDAT2
In/Output
CPU Data bus
11
HDAT3
In/Output
CPU Data bus
12
HDAT4
In/Output
CPU Data bus
13
HDAT5
In/Output
CPU Data bus
14
HDAT6
In/Output
CPU Data bus
15
HDAT7
In/Output
CPU Data bus
16
VSS
–
Digital GND
17
VDD
–
Power +3.3V
18
EXPAL (0)
In/Output
General-use input/output terminal Gr.A
19
EXPAL (1)
In/Output
General-use input/output terminal Gr.A
20
EXPAL (2)
In/Output
General-use input/output terminal Gr.A
21
EXPAL (3)
In/Output
General-use input/output terminal Gr.A
22
EXPAU (0)
In/Output
General-use input/output terminal Gr.A
23
EXPAU (1)
In/Output
General-use input/output terminal Gr.A
24
VSS
–
Digital GND
25
VDD
–
Power +3.3V
26
EXPAU (2)
In/Output
General-use input/output terminal Gr.A
27
EXPAU (3)
In/Output
General-use input/output terminal Gr.A
28
EXPBL (0)
In/Output
General-use input/output terminal Gr.B
29
EXPBL (1)
In/Output
General-use input/output terminal Gr.B
30
EXPBL (2)
In/Output
General-use input/output terminal Gr.B
31
EXPBL (3)
In/Output
General-use input/output terminal Gr.B
32
VSS
–
Digital GND
33
VDD
–
Power +3.3V
34
EXPBU (0)
In/Output
General-use input/output terminal Gr.B
35
EXPBU (1)
In/Output
General-use input/output terminal Gr.B
36
EXPBU (2)
In/Output
General-use input/output terminal Gr.B
37
EXPBU (3)
In/Output
General-use input/output terminal Gr.B
38
EXPC (0)
In/Output
General-use input/output terminal Gr.C
39
EXPC (1)
In/Output
General-use input/output terminal Gr.C
40
EXPC (2)
In/Output
General-use input/output terminal Gr.C
41
VSS
–
Digital GND
42
EXPC (3)
In/Output
General-use input/output terminal Gr.C
43
EXPC (4)
In/Output
General-use input/output terminal Gr.C
44
EXPC (5)
In/Output
General-use input/output terminal Gr.C
45
EXPD (0)
In/Output
General-use input/output terminal Gr.D
46
EXPD (1)
In/Output
General-use input/output terminal Gr.D
47
EXPD (2)
In/Output
General-use input/output terminal Gr.D
48
VSS
–
Digital GND
49
VDD
–
Power +3.3V
50
EXPD (3)
In/Output
General-use input/output terminal Gr.D
51
EXPD (4)
In/Output
General-use input/output terminal Gr.D
52
EXPD (5)
In/Output
General-use input/output terminal Gr.D
53
BUFDO
Output
Buffer output D
54
BUFDI
Input
Buffer input D
55
SBUFBO
Output
Schmidt buffer output B
56
SBUFBI
Input
Schmidt buffer input B
57
SBUFAO
Output
Schmidt buffer output A
58
SBUFAI
Input
Schmidt buffer input A
59
MRST
Input
Reset terminal
60
MODE
Input
Mode selection terminal
61
BUFCO
In/Output
Buffer output C
62
TEST
Input
Test terminal (for Epson)
63
BUFCI
Input
Buffer input C
64
VSS
–
Digital GND
Terminal
Terminal name
In/Output
Function
11-11
DV-700S
DV-760S/H
DV-760S/H
Pin1~15 ........ There is a possibility of simultaneous change.
Operating frequency: Approx. 10 MHz
Pin18~47 ..... There is a possibility of simultaneous change.(Static signal)
Operating frequency: Approx. 1 MHz
Pin50~57 ..... There is almost no possibility of simultaneous change.
Operating frequency: Approx. 1 MHz
Pin63 ............ Not used
• Block Diagram
Data Buffer
Latch D
Data Buffer
Latch C
Data Buffer
Latch B
Data Buffer
Latch A
Data Buffer
R/W CTL
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VDD
EXPD(3)
EXPD(4)
EXPD(5)
BUFDO
BUFDI
SBUFBO
SBUFBI
SBUFAO
SBUFAI
MRST
MODE
BUFCO
TEST
BUFCI
VSS
VDD
SOUT(3)
SOUT(4)
SOUT(5)
MRST
MODE
SEL
TEST
CK
VSS
VSS
EXPD(2)
EXPD(1)
EXPD(0)
EXPC(5)
EXPC(4)
EXPC(3)
VSS
EXPC(2)
EXPC(1)
EXPC(0)
EXPBU(3)
EXPBU(2)
EXPBU(1)
EXPBU(0)
VDD
VSS
SOUT(2)
SOUT(1)
SOUT(0)
S2(5)
S2(4)
S2(3)
VSS
S2(2)
S2(1)
S2(0)
Q2(7)
Q2(6)
Q2(5)
Q2(4)
VDD
VSS
EXPBL(3)
EXPBL(2)
EXPBL(1)
EXPBL(0)
EXPAU(3)
EXPAU(2)
VDD
VSS
EXPAU(1)
EXPAU(0)
EXPAL(3)
EXPAL(2)
EXPAL(1)
EXPAL(0)
VDD
VSS
Q2(3)
Q2(2)
Q2(1)
Q2(0)
Q1(7)
Q1(6)
VDD
VSS
Q1(5)
Q1(4)
Q1(3)
Q1(2)
Q1(1)
Q1(0)
VDD
VDD
HADR0
HADR1
HADR2
HCS
HWR
HRD
HDAT0
HDAT1
HDAT2
HDAT3
HDAT4
HDAT5
HDAT6
HDAT7
VSS
VDD
D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
S1(0)
S1(1)
S1(2)
S1(3)
S1(4)
S1(5)
VSS
In/Output Pin
Exclusive-use pin
In/Output Pin
In/Output Pin
In/Output Pin
In/Output Pin
Output:
Open drain
Input Pin
In/Output Pin
Output: Open drain
11-12. IC601 IX1521GE
SOURCE DECODER
Pin No.
Pin name
Type
Direction
Function
22
HA[3:0]
I
I
Address bus input for microcomputer connection.
24-26
Used for register access and so on
HTYPE = L
It works as HR/W#(read/write) input terminal for connection to Motorola
HTYPE = L
It works as HR/W#(read/write) input terminal for connection to Motorola
27
HWR#
I
I
type microcomputer.
(HR/W#)
HTYPE = H
It works as HWR# (write) input terminal for connection to general purpose
microcomputer.
It works as HWR# (write) input terminal for connection to general purpose
microcomputer.
29
HCS#
I
I
Chip select input for connection to microcomputer
HTYPE = L
It works as HDS#(data strobe) input terminal for connection to Motorola
HTYPE = L
It works as HDS#(data strobe) input terminal for connection to Motorola
30
HRD#
I
I
type microcomputer.
(HDS#)
HTYPE = H
It works as HRD# (read) input terminal for connection to general purpose
microcomputer.
Bit stream input ready output terminal If the bit stream is input from
microcomputer, the terminal is bored.
For 3-state output, connect the pull-up resistor.
HRDY = L
It works as HRD# (read) input terminal for connection to general purpose
microcomputer.
Bit stream input ready output terminal If the bit stream is input from
microcomputer, the terminal is bored.
For 3-state output, connect the pull-up resistor.
HRDY = L
31
HRDY
3-S
O
Bit stream can not be input.
HRDY = H
The number of bytes which are set by CodBurstLen parameter can be
transferred from the microcomputer. During the time from transfer start of
the number of set bytes to transfer end, the terminal varies in 3 states.
HRDY = H
The number of bytes which are set by CodBurstLen parameter can be
transferred from the microcomputer. During the time from transfer start of
the number of set bytes to transfer end, the terminal varies in 3 states.
Microcomputer interface
11-12
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