Sharp DV-760H (serv.man3) Service Manual ▷ View online
DV-700S
DV-760S/H
DV-760S/H
11-5. IC402 IX1474GE DEM/ECC (DVD)
Pin No.
Terminal name
I/O
Operation function
Remarks
1
DPCK1
I
Signal processing reference clock input.
0.5-3.3Vp-p Feedback
resistor built in.
resistor built in.
2
DVDD3
–
Digital power. (3.3V)
For logic cell
3
SVCK1
I
Servo reference clock input. (Oscillation circuit input terminal)
3.3V-I/F Feedback
4
SVCK0
O
Servo reference clock output. (Oscillation circuit input terminal)
resistor built in.
5
DVSS
–
Digital power. (0V)
For logic cell
6
DVDD2
–
Digital power. (3.3V)
For logic cell
7
N.C.
–
User use prohibited.
Open
8
HDWR
I
MPU write signal.
TTL level
9
HDRD
I
MPU read signal.
TTL level
10
ECCCS
I
MPU chip selection.
TTL level
11
D8
I/O
MPU data bus.
TTL level
12
D9
I/O
MPU data bus.
TTL level
13
D10
I/O
MPU data bus.
TTL level
14
D11
I/O
MPU data bus.
TTL level
15
D12
I/O
MPU data bus.
TTL level
16
D13
I/O
MPU data bus.
TTL level
17
D14
I/O
MPU data bus.
TTL level
18
D15
I/O
MPU data bus.
TTL level
19
DVSS
–
Digital power. (0V)
For I/O cell
20
DVDD5
–
Digital power. (5V)
For I/O cell
21
HINT
O
MPU interruption signal. (Occurrence of interruption = “L”)
OPEN DRAIN
22
HA0
I
MPU address bus.
TTL level
23
HA1
I
MPU address bus.
TTL level
24
PLCK
I/O
Read channel clock input/output terminal.
25
ED0
–
User use is prohibited (N.C.) since it is for shipping adjustment.
Open
26
ED1
–
27
ED2
–
28
ED3
–
29
ED4
–
30
ED5
–
31
ED6
–
32
ED7
–
33
TEST
I
For shipping adjustment.
Set to “L”
34
PDON
O
PLL phase error signal output. (Negative polarity)
35
PDOP
O
PLL phase error signal output. (Positive polarity)
36
RLLD
O
RLL detection result output.
37
LPFN
I
PLL loop filter amp. reverse input.
38
LPFO
O
PLL loop filter amp. output.
39
VCOF
O
VCO filter terminal.
40
SLCO
O
Built-in comparator reference voltage output terminal.
41
AVSS
–
Analog power. (0V)
42
AVR
O
Non-PLL system analog reference potential. (1.65V)
43
VRC
–
Resistance division point potential. (For analog reference
potential generation: 1.65)
potential generation: 1.65)
44
PVR
O
PLL system analog reference potential. (1.65V)
45
AVDD
–
Analog power. (3.3V)
46
RVR2
–
2nd reference voltage. (For capacitor connection)
47
RVDD
–
Exclusive-use power terminal. (3.3V)
48
RFIN
I
RF signal input.
49
RVSS
–
Exclusive-use power terminal. (0V)
50
RVR1
–
1nd reference voltage. (For capacitor connection)
51
DVR
I
DMO reference potential. (1.65V recommended)
52
DMO
O
Disc equalizer output for DVD. (Triple value PWM + HiZ)
53
RASN
O
External RAM row address selection. (Negative logic)
54
CASN
O
External RAM row address selection. (Negative logic)
11-5
DV-700S
DV-760S/H
DV-760S/H
Pin No.
Terminal name
I/O
Operation function
Remarks
55
MOEN
O
External RAM output permission signal.
56
MWEN
O
External RAM read/write selection.
57
DVSS
–
Digital power. (0V)
For logic cell
58
DVDD3
–
Digital power. (3.3V)
For logic cell
59
MA9
O
External RAM address bus.
60
MA8
O
External RAM address bus.
61
MA7
O
External RAM address bus.
62
MA6
O
External RAM address bus.
63
MA5
O
External RAM address bus.
64
MA4
O
External RAM address bus.
65
MA3
O
External RAM address bus.
66
MA2
O
External RAM address bus.
67
MA1
O
External RAM address bus.
68
MA0
O
External RAM address bus.
69
DVSS
–
Digital power. (0V)
For I/O cell
70
DVDD5
–
Digital power. (5V)
For I/O cell
71
MD7
I/O
External RAM data bus.
TTL level
72
MD6
I/O
External RAM data bus.
TTL level
73
MD5
I/O
External RAM data bus.
TTL level
74
MD4
I/O
External RAM data bus.
TTL level
75
MD3
I/O
External RAM data bus.
TTL level
76
MD2
I/O
External RAM data bus.
TTL level
77
MD1
I/O
External RAM data bus.
TTL level
78
MD0
I/O
External RAM data bus.
TTL level
79
SD7
O
MPEG data output.
80
SD6
O
MPEG data output.
81
SD5
O
MPEG data output.
82
SD4
O
MPEG data output.
83
DVSS
–
Digital power. (0V)
For logic cell
84
DVDD3
–
Digital power. (3.3V)
For logic cell
85
SD3
O
MPEG data output.
86
SD2
O
MPEG data output.
87
SD1
O
MPEG data output.
88
SD0
O
MPEG data output.
89
SERR
O
MPEG data reliability flag. (Data error: “L”)
90
SOSO
O
MPEG output sector sync signal. (Sector top: “L”)
91
SVAL
O
MPEG data effective flag. (Effective state: “L”)
92
SDCK
O
MPEG data transfer clock.
93
DVSS
–
Digital power. (0V)
For logic cell
94
SREQ
I
MPEG data request flag. (Request state: “L”)
TTL level
95
RSTN
I
Hard reset input. (Reset state: “L”)
96
DVDD3
–
Digital power. (3.3V)
For logic cell
97
STDA
O
Operation state monitor data.
Common with PWM.
(Output synchronizing with SDCK fall)
98
STCK
O
Operation state monitor sync signal. (Data top bit: “L”)
Common with PWM.
99
UPWM
O
General-use PWM output.
4mA, 5V-I/F
100
DVSS
–
Digital power. (0V)
For logic cell
11-6
DV-700S
DV-760S/H
DV-760S/H
11-6. IC501 IX1614GE
FLASH
Symbol
Type
Name and function
Byte selection address: When the device is in the x8 mode, the low or high order byte is
DQ
15
/A
-1
Input
selected. It is not used in the x16 mode.
(If BYTE# is high, DQ
(If BYTE# is high, DQ
15
/A
-1
input circuit does not operate.)
A
0
-A
12
Input
Word selection address: Selection of one word of 16k byte block. These addresses are
latched during data wiring operation.
latched during data wiring operation.
A
13
-A
17
Input
Block selection address: Selection of 1/32 erase block. These addresses are latched
during data writing, erasing and lock block operation.
Low order byte data input/output: Command user interface writing cycle data and command
during data writing, erasing and lock block operation.
Low order byte data input/output: Command user interface writing cycle data and command
DQ
0
-DQ
7
Input/Output
input. Various data read memory identifier and status data output Chip nonselection or output
disable: Float state
disable: Float state
DQ
8
-DQ
15
Input/Output
High order byte data input/output: The function is the same as that of low order byte data
input/output. Operative only in x16 mode. x8 mode: Float state DQ
input/output. Operative only in x16 mode. x8 mode: Float state DQ
15
/A
-1
is address.
CE#
Input
Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Chip becomes active only when CE# is “Low”.
Reset/Power down: If RP# is set to “Low”, the control circuit is initialized when power is turned
on. Hence, the RP#pin is set to “Low”. When power is turned on or off or in case of fluctuation it
Chip becomes active only when CE# is “Low”.
Reset/Power down: If RP# is set to “Low”, the control circuit is initialized when power is turned
on. Hence, the RP#pin is set to “Low”. When power is turned on or off or in case of fluctuation it
RP#
Input
is kept at “Low” so as to protect data from noise. When RP# is in “Low” state, the device is in
deep power down state. 480 ns is required to recover from the deep power down state. If the RP#
pin becomes “Low”, the whole chip operation is interrupted and reset. After recovery the device is set
to array read state.
deep power down state. 480 ns is required to recover from the deep power down state. If the RP#
pin becomes “Low”, the whole chip operation is interrupted and reset. After recovery the device is set
to array read state.
OE#
Input
Output enable: When OE# is set to “Low”, data is output from the DQ pin. When OE# is
set to “High”, the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is controlled.
set to “High”, the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is controlled.
WE#
Input
In “Low” state WE# becomes active. At rise edge the address and data are fetched.
Ready/busy: The state of internal write state machine is output. In “Low” state it is indicated that the
Ready/busy: The state of internal write state machine is output. In “Low” state it is indicated that the
RY/BY#
Output
write state machine is in operation. If the write state machine waits for next operation instruction, erase
is suspended or it is in deep power down state, the RY/BY# pin is in float state.
Byte enable: When BYTE# is set to “Low”, the device is set to the x8 mode. At this time the
is suspended or it is in deep power down state, the RY/BY# pin is in float state.
Byte enable: When BYTE# is set to “Low”, the device is set to the x8 mode. At this time the
BYTE#
Input
DQ
8
-DQ
15
pin becomes float state. Address A
-1
selects high order/low order byte.
When BYTE# is “High”, the device is set to the x16 mode. The A
-1
input circuit is disabled.
Vpp
Write/erase power supply: 5.0
±
0.5V is applied during writing/erasing.
Vcc
Device power supply: 5.0
±
0.5V
GND
Ground
NC
Nonconnection
• Block Diagram
ID
Register
CSR
ESRs
DQ
8-15
DQ
0-7
OUTPUT MULTIPLEXER
Program Erase
Voltage Switch
BYTE#
CUI
WSM
16-KBYTE
Block 31
16-KBYTE
Block 30
16-KBYTE
Block 1
16-KBYTE
Block 0
CE#
OE#
WE#
RP#
RY/BY#
V
PP
V
CC
GND
Y GATING/SENSING
X-DECODER
Y-DECODER
Input
Buffer
ADDRESS
QUEUE
LATCHES
ADDRESS
COUNTER
COUNTER
A
-1.0~17
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
I/O Logic
DATA
QUEUE
REGISTER
Register
Data
Comparator
11-7
DV-700S
DV-760S/H
DV-760S/H
11-7. IC504 IX1478GE
SYSCON
MD
2
V
cc
V
cc
V
cc
V
cc
V
cc
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
PD
7
/D
15
PD
6
/D
14
PD
5
/D
13
PD
4
/D
12
PD
3
/D
11
PD
2
/D
10
PD
1
/D
9
PD
0
/D
8
PE
7
/D
7
PE
6
/D
6
PE
5
/D
5
PE
4
/D
4
PE
3
/D
3
PE
2
/D
2
PE
1
/D
1
PE
0
/D
0
PA
7
/A
23
/IRQ7
PA
6
/A
22
/IRQ6
MD
1
MD
0
PF
7
/ø
PF
6
/AS
PF
5
/RD
PF
4
/HWR
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
XTAL
STBY
RES
WDTOVF
NMI
PF
3
/LWR
PF
1
/BACK
PF
0
/BREQ
PG
4
/CS0
PG
3
/CS1
PG
2
/CS2
PG
1
/CS3
PG
0
/CAS
P6
7
/CS7/IRQ3
P6
6
/CS6/IRQ2
P6
5
/IRQ1
P6
4
/IRQ0
P6
3
/TEND1
P6
2
/DREQ1
P6
1
/TEND0/CS5
P6
0
/DREQ0/CS4
PF
2
/LCAS/WAIT/BFEQO
P1
0
/PO8/TIOCA0/DACK0
P1
1
/PO9/TIOCB0/DACK1
P1
2
/PO10/TIOCC0/TCLKA
P1
3
/PO11/TIOCD0/TCLKB
P1
4
/PO12/TIOCA1
P1
5
/PO13/TIOCB1/TCLKC
P1
6
/PO14/TIOCA2
P1
7
/PO15/TIOCB2/TCLKD
P2
0
/PO0/TIOCA3
P2
1
/PO1/TIOCB3
P2
2
/PO2/TIOCC3
P2
3
/PO3/TIOCD3
P2
4
/PO4/TIOCA4
P2
5
/PO5/TIOCB4
P2
6
/PO6/TIOCA5
P2
7
/PO7/TIOCB5
P4
7
/AN7/DA1
P4
6
/AN6/DA0
P4
5
/AN5
P4
4
/AN4
P4
3
/AN3
P4
2
/AN2
P4
1
/AN1
P4
0
/AN0
V
ref
AV
cc
AV
ss
PA
5
/A
21
/IRQ5
PA
4
/A
20
/IRQ4
PA
3
/A
19
PA
2
/A
18
PA
1
/A
17
PA
0
/A
16
PB
7
/A
15
PB
6
/A
14
PB
5
/A
13
PB
4
/A
12
PB
3
/A
11
PB
2
/A
10
PB
1
/A
9
PB
0
/A
8
PC
7
/A
7
PC
6
/A
6
PC
5
/A
5
PC
4
/A
4
PC
3
/A
3
PC
2
/A
2
PC
1
/A
1
PC
0
/A
0
P3
5
/SCK1
P3
4
/SCK0
P3
3
/RxD1
P3
2
/RxD0
P3
1
/TxD1
P3
0
/TxD0
P5
0
P5
1
P5
2
P5
3
/ADTRG
ROM *
RAM
TPU
PPG
SCI
WDT
DMAC
DTC
H8S/2000 CPU
D/A converter
A/D converter
Clock oscillator
Interruption
controller
Bass Controller
Port D
Port F
Port G
Port 6
Port 5
Port 3
Port C
Port B
Port A
Port E
Port 1
Port 2
Port 4
Internal data bus
Peripheral data bus
Peripheral address bus
Internal address bus
131072 WORDS
X 8 BYS
X 8 BYS
(1024 ROWS
X126 COLUMNS
X8 BL9OCKS)
X126 COLUMNS
X8 BL9OCKS)
8
7
6
5
4
3
31
28
27
12
10
9
23
25
26
11
2
13
14
15
17
18
19
20
21
29
22
30
24
32
16
A4
A5
A6
A7
A12
A14
A16
A15
A13
A8
A0
A2
A3
A1
A9
A10
A11
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
R/W
CE1
CE2
OE
VDD
(5V)
(5V)
GND
(0V)
(0V)
ADDRESS INPUT
BUFFER
ROW
DECORDER
SENSE AMP.
OUTPUT
BUFFER
DATA INPUT
BUFFER
CLOCK
GENERATOR
COLUMN
DECODER
ADDRESS INPUT
BUFFER
ADDRESS INPUT
BUFFER
BLOCK
DECODER
11-8. IC506 IX1618GE
1M SRAM
11-8
Click on the first or last page to see other DV-760H (serv.man3) service manuals if exist.