Sharp DV-760H (serv.man3) Service Manual ▷ View online
DV-700S
DV-760S/H
DV-760S/H
Pin No.
Terminal name
I/O
Operation function
1
CVBS/Cb/B1
O
Analog composite video signal output or Cb or B signal output current drive (positive)
2
CVBS/Cb/B1
O
Analog composite video signal output or Cb or B signal output current drive (negative)
3
CVBS/Cb/B1 Vdd
Power Supply for CVBS / Cb/B DAC1 circuit
4
Y/G 1
O
Analog luminance or G signal output current drive (positive)
5
Y/G 1
O
Analog luminance or G signal output current drive (negative)
6
Y/G 1Vdd
Power Supply for Y/G DAC1 circuit
7
C/Cr/R 1
O
Analog chrominance signal output or Cr or R signal output current drive (positive)
8
C/Cr/R 1
O
Analog chrominance signal output or Cr or R signal output current drive (negative)
9
C/Cr/R 1Vdd
Power Supply for C/Cr/R DAC1 circuit
10
DA Vss
Ground for DAC circuit
11
Ibias 1
O
Reference current for the 1st set of 3 DACs
12
VRef 1
Reference full scale voltage for the 1st set of 3 DACs
13
DA Vdd
Power Supply for DACs
14
VRef 2
Reference full scale voltage for the 2nd set of 3 DACs
15
Ibias 2
O
Reference current for 2nd set of the 3 DACs
16
NC
No connect to pin
17
CVBS/Cb/B2
O
Analog composite video signal output or Cb or B signal output current drive (positive)
18
CVBS/Cb/B2
O
Analog composite video signal output or Cb or B signal output current drive (negative)
19
CVBS/Cb/B2 Vdd
Power Supply for CVBS / Cb/B DAC2 circuit
20
Y/G 2
O
Analog luminance or G signal output current drive (positive)
21
Y/G 2
O
Analog luminance or G signal output current drive (negative)
22
Y/G Vdd
Power Supply for Y/G DAC2 circuit
23
C/Cr/R 2
O
Analog chrominance signal output or Cr or R signal output current drive (positive)
24
C/Cr/R 2
O
Analog chrominance signal output or Cr or R signal output current drive (negative)
25
C/Cr/R 2Vdd
Power Supply for C/Cr/R DAC2 circuit
26
ChipA
I2C chip address select {0 : 40(hex)/41(hex) 1 : 1D(hex)/1E(hex)}
27
TEST
I
TEST pin (Ground)
28
DVss
Ground for Digital circuit
29
CLOCK
I
27MHz clock input
30
DVdd
Power Supply for Digital circuit
31
Reset
I
Reset signal, active LOW
32
PAL/NTSC
I
NTSC/PAL select. This pin is sampledonly at Reset.(NTSC : Low PAL : High)
33
SO
z(O)
In SPI mode, serial data output / In I2C mode, grounded.
34
SDA/SI
I/O(I)
Serial data input, Open drain output / If SPI mode, serial data input
35
SCL/SCK
I
Serial clock
36
SEL
I/(I)
Connect to Ground / If SPI mode, this pin is chip select
37
DVdd
Power supply for Digital circuit
38
DVss
Ground for Digital circuit
39-46
DVIA7-0
I/O
8-bit Multiplexd Y/Cr/Cb 4:2:2 data (ITU Rec656/601) input (DVIA) or Multiplexd Y data
(ITU-Rec656/601) input in 16-bit input mode
(ITU-Rec656/601) input in 16-bit input mode
47
Vmute
I
Video mute on Reset (0: normal, 1: mute)
48
C/Fsync/VBI
I/O
Csync/Frame sync input/output
49
F/Vsync
I/O
Frame sync or Vertical sync input/output
50
Hsync
I/O
Horizontal sync input/output
51
A/B sel
I
Switch control for 8-bit x 2 Mutiplexed 4:2:2 data (ITU Rec656/601) input (DVIA) or (DVIB)
52-55
DVIB7-4
I/O
8-bit Multiplexed 4:2:2 data (ITU Rec656-601) input (DVIB), or Multiplexed Cr/Cb data
(ITU Rec656/601) input in 16-bit input mode
(ITU Rec656/601) input in 16-bit input mode
56
DVss
Ground for Digital circuit
57
DVdd
Power Supply for Digital circuit
58-61
DVIB3-0
I/O
Multiplexed 4:2:2 data (ITU Rec656/601) input (DVIB), or Multiplexed Cr/Cb data
(ITU Rec656/601) input in 16-bit input mode
(ITU Rec656/601) input in 16-bit input mode
62
TP
I/O
Test data input/output (Grounded)
63,64
NC
No connect to pin (Ground)
11. IC FUNCTION LIST
11-1. IC201 MC44724A
DIGITAL VIDEO ENCODER
11-1
DV-700S
DV-760S/H
DV-760S/H
Pin No.
Terminal name
I/O
Operation function
1
EIN
I
RF signal input. Input of RF signal output of optical pickup.
2
GND1
–
Ground
3
S/DUAL
I
Single layer/dual layer selection signal input.
4
AIN
I
RF signal input. Input of RF signal output of optical pickup.
5
BIN
I
RF signal input. Input of RF signal output of optical pickup.
6
CIN
I
RF signal input. Input of RF signal output of optical pickup.
7
DIN
I
RF signal input. Input of RF signal output of optical pickup.
8
VrefIN
I
Reference voltage input. (2.1V)
9
FIN
I
RF signal input. Input of RF signal output of optical pickup.
10
GAINsel1
I
Amp gain selection input 1.
11
VCC1
–
Power terminal. (5.0V)
12
GAINsel2
I
Amp gain selection input 2.
13
FOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
14
EOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
15
DOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
16
COUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
17
BOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
18
AOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
19
VCC2
–
Power terminal. (5.0V)
20
RFPOUT
O
Data read signal output. The same phase as MIXIN.
21
RFNOUT
O
Data read signal output. Reverse phase with respect to MIXIN.
22
MIXIN
I
Data read signal input.
23
MIXOUT
O
Data read signal output.
24
GND2
–
Ground
• Block Diagram
• Mode selection table
GAINsel1 (Terminal 10)
GAINsel2 (Terminal 12)
Amp gain
L
L
+6dB
H, OPEN
L
-2dB
L
H, OPEN
+2dB
H, OPEN
H, OPEN
-6dB
Amp. gain selection
Layer
S/DSEL (Terminal 3)
Amp gain
Single
L, OPEN
0dB
Dual
H
+10dB
Single layer/dual layer selection
11-2. IC301 IX1461GE
RF PRE AMP.
H, V
Y
demux
Cb
Cr
Modulator
subcarrier
gen
off_set
0
0
0
CGMS,
WSS gen
CC_gen
Sync_generator
BG
copy
protection
bus
bus
TEST
I2C/SPI
BIAS
DAC
DAC
DAC
30 37, 57
28
51
38, 56
39~46
52~55, 58~61
DVdd
DVss
DVIA [7:0]
DVIB [7:0]
A/B_sel
62
TP
29
Clock
26
Chip A
31
Reset
32
33
PAL/NTSC
SO
34
SDA/SI
35
SCL/SCK
36
SEL
27
TEST
10
DAVss
13
DAVdd
15
Ibias 2
14
Vref 2
24
C/Cr/R 2
23
C/Cr/R 2
18
CVBS/Cb/B 2
17
CVBS/Cb/B 2
21
Y/G 2
20
Y/G 2
11
Ibias 1
12
Vref 1
8
C/Cr/R 1
7
C/Cr/R 1
2
CVBS/Cb/B 1
1
CVBS/Cb/B 1
5
Y/G 1
4
Y/G 1
9
C/Cr/R 1Vdd
3
CVBS/Cb/B 1Vdd
6
Y/G 1Vdd
25
C/Cr/R 2Vdd
19
CVBS/Cb/B 2Vdd
22
Y/G Vdd
50
Hsync
49
F/Vsync
48
C/Fsync/VBI
MC44724/5A
BIAS
DAC
DAC
Output Selector
DAC
0
0
0
0
0
0
0
RGB matrix
11-2
DV-700S
DV-760S/H
DV-760S/H
1
GND
–
GND terminal.
–
2
P2TP
I
TE+input (CD)
VrA
3
P2TN
I
TE–input (CD)
VrA
4
LDO2
O
Drive ouput
–
5
MDI2
I
Monitor input
–
6
VrA
O
Analog VREF
2.1[V]
7
VrD
O
Digital VREF
–
Vdd 1/2
8
Vdd
I
Power terminal
4.2V (3.3V)
9
DPAC
–
DPD AC combination capacity 1
–
10
DPBD
–
DPD AC combination capacity 2
–
11
DPD1
–
DPD integral capacity 1
–
12
DPD2
–
DPD integral capacity 2
–
13
SCB
I
Control line (Bit clock)
2.2[V]
14
SCL
I
Control line (Latch signal)
2.2[V]
15
SCD
I
Control line (Sirial Data)
2.2[V]
16
VRCK
I
Reference clock input
2.3[V]
When frequency is increased, the
filters excepting the servo LPF are
shifted to high frequency side.
filters excepting the servo LPF are
shifted to high frequency side.
17
VCKF
–
Capacity for time constant adjustment
–
18
VccP
–
Power terminal
–
19
LVL
O
Servo addition output
Vrd x (1/2)
20
TEO
O
TE output
VrD
21
FEO
O
FE output
VrD
22
DFTN
I
DPD difect
–
Low DPD output: Mute
23
VccS
–
Power terminal (servo)
–
24
RPZ
O
RF ripple center voltage
VrD
25
RPO
O
RF ripple output
VrD
26
RPB
O
RF ripple bottom
–
27
RPP
O
RF ripple peak
–
28
RFO
O
Equalizing RF output
2.3[V]
29
NC
–
NC terminal
–
To be connected to GND
30
NC
–
NC terminal
–
To be connected to GND
31
VccR
–
Power terminal (RF)
–
32
DPDB
I
Pit depth adjustment
VrD
When D PDB is raised, the A/B
side delay increases.
side delay increases.
33
TEB
I
TE balance
VrD
When TEB is raised, the TP side
gain increases and the A+C side
delay increases.
gain increases and the A+C side
delay increases.
34
FEB
I
FE balance
VrD
When FEB is raised, the A+C (FP)
side gain increases.
side gain increases.
35
PSC
I
VRCK frequency division ON/OFF
–
High: Frequency division OFF
36
Vcc2
–
Power terminal
–
37
NC
–
NC terminal
VrD
To be connected to VrD, or to GND
through C
through C
38
EQD
I
Group delay correction
VrD
When EQD is raised, the group
delay increases at the right side.
delay increases at the right side.
39
GND2
–
GND terminal.
–
40
RFDC
–
DC feedback capacity
–
Pin No. Terminal name
I/O
Operation function
Terminal DC Voltage(TYP.)
Remarks
11-3. IC303 IX1517GE
RF SIGNAL PROCESSOR
• Block Diagram
24
23
22
21
20
19
18
17
16
15
14
13
1
9
8
7
6
5
4
3
2
10
12
11
MIX
EIN
CIN
BIN
AIN
S/DUAL
GND1
FIN
VrefIN
DIN
DOUT
FOUT
VCC1
GAINsel1
GAINsel2
RFPOUT
VCC2
AOUT
BOUT
COUT
EOUT
RFNOUT
GND2
MIXOUT
MIXIN
11-3
DV-700S
DV-760S/H
DV-760S/H
41
RFA
O
RF total addition output
2.2[V]
42
EQB
I
Boost adjustment
VrD
When EQB is raised, the boost increases.
43
EQF
I
Frequency adjustment
VrD
When EQF is raised, shift to the
high frequency side occurs.
high frequency side occurs.
44
MDI1
I
Monitor input
–
45
LDO1
O
Drive output
–
46
P1TN
I
TE–input (DVD)
VrA
47
P1TP
I
TE+input (DVD)
VrA
48
NC
–
NC terminal
–
To be connected to GND
49
P1FN
I
FE–input (DVD)
VrA
50
P1FP
I
FE+input (DVD)
VrA
51
LDP1
I
APC polarity 1
–
Positive polarity when this terminal
is connected to Vcc.
is connected to Vcc.
52
P1DI
I
D input (DVD)
53
P1CI
I
C input (DVD)
VrA
54
P1BI
I
B input (DVD)
VrA
55
P1AI
I
A input (DVD)
VrA
56
GNDR
–
GND terminal (RF)
–
57
LDP2
I
APC polarity 2
–
Positive polarity when this terminal
is connected to Vcc.
is connected to Vcc.
58
P2AI
I
A input (CD)
VrA
59
P2BI
I
B input (CD)
VrA
60
P2CI
I
C input (CD)
VrA
61
P2DI
I
D input (CD)
VrA
62
GNDS
–
GND terminal (Servo)
–
63
P2FP
I
FE+input (CD)
VrA
64
P2FN
I
FE–input (CD)
VrA
Pin No. Terminal name
I/O
Operation function
Terminal DC Voltage(TYP.)
Remarks
Terminal
Terminal name
Function
10~13,16~20,9
A0~A8,A9R
Address input
8
RAS
Row address strobe
23
CAS
Column address strobe
2~5,24~27
DQ1~DQ8
Data input/Data output
22
OE
Output enable
7
WE
Light enable
1, 14
Vcc
Power (5V)
15, 28
Vss
Ground (0V)
6, 21
NC
Not connected
11-4. IC401 IX1484GE
4M DRAM
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
DPDB
VccR
NC
NC
RFO
RPP
RPB
RPO
RPZ
VccS
DFTN
FEO
TEO
LVL
VccP
VCKF
NC
P1TP
P1TN
LDO1
MDI1
EQF
EQB
RFA
RFDC
GND2
EQD
NC
Vcc2
PSC
FEB
TEB
GND
P2TP
P2TN
LDO2
MDI2
VrA
VrD
Vdd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
VRCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
APC1
sel-RF
R-gain
Adjust
EQ
F-gain
Adjust
Adjust
F-gain
Adjust
Adjust
RF Ripple
creation
FE creation
DPDTE
creation
FE-gain
Adjust
TE-gain
Adjust
Level detect
T-gain
Adjust
Adjust
3BTE creation
APC2
B U S
Time
constant
adjustment
sel-PD
sel-PD
sel-PD
mode-TE
sel-FE
sel-IC
sel-TE
sel-DPD
sel-LVL
• Block Diagram
11-4
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