Sharp DV-720H (serv.man19) Service Manual ▷ View online
25
DV-720S/DV-720S(K)
DV-720H
DV-720H
Pin No.
Pin name
Type
Direction
Function
31
HRD#—HDS#
I
I
Input
In host protocol type A (HTYPE=GNDP): HDS#. Data strobe input (active low).
In host protocol type B (HTYPE=VDDP): HRD#. Host read input (active low).
In host protocol type B (HTYPE=VDDP): HRD#. Host read input (active low).
33
HRDY
3-S
O (p.d.)
Reset: output (low)
Standby: 3-S
Standby: 3-S
Host ready output. When this signal is tri-stated (i.e., it requires a pull-up resistor), up to SysConfig.CodBurstLen
bytes of code can be written to the Decoder with no need to poll its condition in between. When HRDY is low during a
host access, the Decoder may still receive at least two additional bytes of code without corrupting the data.
bytes of code can be written to the Decoder with no need to poll its condition in between. When HRDY is low during a
host access, the Decoder may still receive at least two additional bytes of code without corrupting the data.
34
HIRQ#
3-S
O (p.u.)
3-S (p.u.)
Interrupt request. This output signal requests an interrupt from the host controller, if one of the events associated to
interrupts occurs, and it is not masked-off. It is de-asserted if the host responds to the interrupt by reading the
interrupt status register, or if the host disables the interrupt, or after RESET.
Deassertion of the HIRQ# output has two modes: De-activated and then tri-stated or directly to is a tri-state condition.
The pin needs external pull-up resistor.
interrupts occurs, and it is not masked-off. It is de-asserted if the host responds to the interrupt by reading the
interrupt status register, or if the host disables the interrupt, or after RESET.
Deassertion of the HIRQ# output has two modes: De-activated and then tri-stated or directly to is a tri-state condition.
The pin needs external pull-up resistor.
36
HACK#
3-S
O (p.u)
Reset: output (high)
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
Host acknowledge output. In protocol A, the Decoder indicates that a read or write cycle is completed by asserting
this output. In protocol B, this signal is used by the Decoder to indicate a wait state that may be used by fast hosts.
In protocol B the host may ignore the HACK# signal.
When this signal is deasserted it is de-activated and then tri-stated. This pin needs an external pull-up resistor.
this output. In protocol B, this signal is used by the Decoder to indicate a wait state that may be used by fast hosts.
In protocol B the host may ignore the HACK# signal.
When this signal is deasserted it is de-activated and then tri-stated. This pin needs an external pull-up resistor.
General Purpose I/O (Host Interface) (3 pins)
Pin No.
Pin name
Type
Direction
Function
147
GPAI/O
3-S
I/O (r.t.)
Reset: input
Standby: 3-S
Standby: 3-S
General purpose input/output pin, monitored/controlled by the audio processor software. After RESET, this pin is
defined as inputs. Their definition can be configured through ADP commands.
defined as inputs. Their definition can be configured through ADP commands.
172
GPSI
I
I
Input
General purpose input, monitored by the system de-multiplexer/video processor software.
171
DPSO
O
O (p.d.)
Reset: output (low)
Standby: 3-S
Standby: 3-S
General purpose output, controlled by the system de-multiplexer/video processor software. After RESET it outputs a
low level.
low level.
DVD-DSP Interface (13 pins)
Pin No.
Pin name
Type
Direction
Function
159
DVDREQ
O
O (p.d.)
Reset: output (low)
Standby: 3-S
Standby: 3-S
DVD-DSP data request output (programmable polarity).
157
DVDVALID
I
I
Input
DVD-DSP data valid input (programmable polarity).
156
DVDSOS
I
I
Input
DVD-DSP start of sector input (programmable polarity).
170
DVDDAT[7]
I
I
Input
169
DVDDAT[6]
168
DVDDAT[5]
167
DVDDAT[4]
166
DVDDAT[3]
164
DVDDAT[2]
162
DVDDAT[1]
161
DVDDAT[0]
DVD-DSP data input bus.
DVD-DSP data input bus.
158
DVDSTRB
I
I
Input
DVD-DSP data bit strobe (clock) input. Programmable polarity.
155
DVDERR
I
I
Input
DVD-DSP error indication input. Programmable polarity.
DV-720S/DV-720S(K)
DV-720H
DV-720H
26
CD-DSP Interface (4 pins)
Pin No.
Pin name
Type
Direction
Function
3
CDERR
I
I/O (r.t.)
Reset: input (p.d.)
4
CDFRM
I
I/O (r.t.)
Standby: 3-S (p.d.)
5
CDDAT
I
I/O (r.t.)
6
CDCLK
I
I/O (r.t.)
When HWID is connected to GNDP, these are the CD-DSP I
2
S input port pins as follows:
CDERR: data error indication input
CDFRM: left/right channel frame input
CDDAT: data input
CDCLK: bit clock input
When HWID is connected to VDDP, these are HD[15:12] of the host data bus, as explained in the host interface pin
description.
CDFRM: left/right channel frame input
CDDAT: data input
CDCLK: bit clock input
When HWID is connected to VDDP, these are HD[15:12] of the host data bus, as explained in the host interface pin
description.
Digital Video Interface (16 pins)
Pin No.
Pin name
Type
Direction
Function
98
VID[7]
3-S
I/O (r.t.)
Reset: 3-S
99
VID[6]
3-S
I/O (r.t.)
Standby: 3-S (p.d.)
100
VID[5]
3-S
I/O (r.t.)
101
VID[4]
3-S
I/O (r.t.)
103
VID[3]
3-S
I/O (r.t.)
105
VID[2]
3-S
I/O (r.t.)
107
VID[1]
3-S
I/O (r.t.)
108
VID[0]
3-S
I/O (r.t.)
Digital video luminance/chrominance outputs, multiplexed in time according to the CCIR656 standard. Used (with
HSYNC and VSYNC) as 10 bits input DACs testing.
HSYNC and VSYNC) as 10 bits input DACs testing.
140
VCLKx2
3-S
I/O (r.t.)
Reset:
Standby: 3-S (p.d.)
Standby: 3-S (p.d.)
Main video clock input or output. 27.000MHz.
89
VCLK
3-S
I/O (r.t.)
Reset:
Standby: 3-S (p.d.)
Standby: 3-S (p.d.)
A division by two of the VCLKx2 signal. This signal is used as data and sync qualifier.
95
HSYNC
3-S
I/O (r.t.)
Reset:
Standby: 3-S (p.d.)
Standby: 3-S (p.d.)
Horizontal sync input/output. Polarity and duration are programmable.
93
VSYNC
3-S
I/O (r.t.)
Reset:
Standby: 3-S (p.d.)
Standby: 3-S (p.d.)
Vertical sync input/output. Polarity and duration are programmable.
96
FI
3-S
I/O (r.t.)
Reset:
Standby: 3-S (p.d.)
Standby: 3-S (p.d.)
Field indication input/output. Polarity is programmable.
92
CBLANK
O
O (p.d.)
Reset: output
Standby: 3-S (p.d.)
Standby: 3-S (p.d.)
Composite blank output. Horizontal and vertical blanking areas and polarity are programmable.
90
VMASTER
I
I
Input
Video master/slave selection input. When this input is high, the Decoder is the video sync master (video SYNC
signals and clocks are output). When it is low, the Decoder is a video Sync slave (video SYNC signals and clocks are
input). This input may be changed only during RESET.
signals and clocks are output). When it is low, the Decoder is a video Sync slave (video SYNC signals and clocks are
input). This input may be changed only during RESET.
91
VDEN#
I
I
Input
Video enable input. When this input is active, the Decoder may output video data on the VID[[7:0] bus. When it is
deasserted, the Decoder tri-states the VID[7:0] bus outputs (although the sync signals are still active). This input may
be changed dynamically and if affects at the next VCLKx2.
deasserted, the Decoder tri-states the VID[7:0] bus outputs (although the sync signals are still active). This input may
be changed dynamically and if affects at the next VCLKx2.
Analog Video Encoder Interface (8 pins)
Pin No.
Pin name
Type
Direction
Function
114
CVBS/G/Y
O
AO
Reset:
(DAC A)
Standby: 3-S
When the Decoder outputs composite video, this line is CVBS
When the Decoder outputs RGB, this line is the Green output
When the Decoder outputs YUV, this line is the U output
When the Decoder outputs RGB, this line is the Green output
When the Decoder outputs YUV, this line is the U output
27
DV-720S/DV-720S(K)
DV-720H
DV-720H
Pin No.
Pin name
Type
Direction
Function
117
Y/R/V
O
AO
Reset:
(DAC B)
Standby: 3-S
When the Decoder outputs the composite video, this line is Y
When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV, this line is the Red output
When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV, this line is the Red output
118
C/B/U
O
AO
Reset:
(DAC C)
Standby: 3-S
When the Decoder outputs the composite video, this line is C
When the Decoder outputs RGB, this line is the Blue output
When the Decoder outputs YUV, this line is the V output
When the Decoder outputs RGB, this line is the Blue output
When the Decoder outputs YUV, this line is the V output
115
CVBS/C
O
AO
Reset:
(DAC D)
Standby: 3-S
When the Decoder outputs any of the types of video, this line can be programmed to output either composite or C.
120
RSET
I
AI
Resistive load for gain adjustment of the DACs
123
VREF
I
AI
Voltage reference for gain adjustment of the DACs
110
DACDISABLE
I
I
Input
DACs disable input. High level force the DACs to float their outputs. Low level selects normal operation of the DACs.
112
COSYNC
3-S
O (p.d.)
Reset: output (low)
Standby: 3-S
Standby: 3-S
Composite sync output. Active only when RGB analog output is selected. Otherwise, the signal is low.
Digital Audio Interface (9 pins)
Pin No.
Pin name
Type
Direction
Function
144
AMCLK
3-S
I/O (p.u.)
Reset: input
Standby: 3-S
Standby: 3-S
Audio Master Clock input/output. 128, 192, 256 or 384 times the sampling frequency (programmable).
146
S/PDIF (AOUT4)
O
O (p.d.)
Reset: input
Standby: 3-S
Standby: 3-S
S/PDIF transmitter output for digital coded or reconstructed audio data. Alternately can be used as a fifth audio
output. After RESET this pin outputs low level.
output. After RESET this pin outputs low level.
152
AOUT[3]
O
O (p.d.)
Reset: output (low)
151
AOUT[2]
Standby: 3-S
150
AOUT[1]
149
AOUT[0]
Serial outputs of digital stereo audio.
Serial outputs of digital stereo audio.
125
AIN
I
I
Input
Serial input of digital stereo audio.
153
ALRCLK
O
O (p.d.)
Reset: output (low)
Standby: 3-S
Standby: 3-S
Digital audio left/right select output for the audio port. Square wave, at the sampling frequency.
Programmable polarity interpretation for input.
Programmable polarity interpretation for input.
154
ABCLK
O
O (p.d.)
Reset: output (low)
Standby: 3-S
Standby: 3-S
Digital audio bit-clock output. Data on AOUT and AIN is output or latched, respectively, with the rising or falling
(programmable) edge of this clock.
(programmable) edge of this clock.
PLL/Clock Interface (6 pins)
Pin No.
Pin name
Type
Direction
Function
132
GCLK
I
I
Input
27.000MHz clock or crystal input for main processing clock generation.
129
GCLK1
I
I
Input
27.000MHz clock input for audio master clock generation. In normal operation must be connected to GCLK.
131
XO
O
AO
Output to a crystal that is connected to GCLK. If a crystal is not used at GCLK, XO must be left not connected.
134
PLLCA
AI/O
PLL Capacitor. In normal operation must be connected to a 47nF capacitor, of which the other node is connected to
GNDA.
GNDA.
127
PLLCFG[1]
I
I
Input
130
PLLCFG[0]
I
I
Input
PLL configuration inputs. Allowed to be changed only during RESET. In normal operation both pins must be
connected to GNDP.
connected to GNDP.
DV-720S/DV-720S(K)
DV-720H
DV-720H
28
SDRAM Interface (35 pins)
Pin No.
Pin name
Type
Direction
Function
87
RAMDAT[15]
3-S
I/O (r.t.)
Reset: input (p.d.)
84
RAMDAT[14]
Standby: 3-S (p.d.)
81
RAMDAT[13]
78
RAMDAT[12]
75
RAMDAT[11]
72
RAMDAT[10]
69
RAMDAT[9]
65
RAMDAT[8]
67
RAMDAT[7]
71
RAMDAT[6]
73
RAMDAT[5]
76
RAMDAT[4]
79
RAMDAT[3]
82
RAMDAT[2]
85
RAMDAT[1]
88
RAMDAT[0]
SDRAM bidirectional data bus.
SDRAM bidirectional data bus.
52
RAMADD[11]
O
O (p.d.)
Reset: output
50
RAMADD[10]
Standby: 3-S
51
RAMADD[9]
48
RAMADD[8]
45
RAMADD[7]
43
RAMADD[6]
40
RAMADD[5]
38
RAMADD[4]
39
RAMADD[3]
42
RAMADD[2]
44
RAMADD[1]
47
RAMADD[0]
SDRAM address bus output.
SDRAM address bus output.
57
RAMRAS#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
SDRAM row select output.
58
RAMCAS#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
SDRAM column select output.
63
PCLK
O
O (p.d.)
Reset: output
Standby: 3-S
Standby: 3-S
SDRAM clock output (Same as internal processing clock).
61
RAMDQM
O
O (p.d.)
Reset: output
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
SDRAM data masking output.
54
RAMCS0#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
SDRAM chip select output for the lower 2MB device.
56
RAMCS1#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
SDRAM chip select output for the upper 2MB device.
59
RAMWE#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
SDRAM write enable output.
Test Signal Interface (3 pins)
Pin No.
Pin name
Type
Direction
Function
138
SCNENBL
I
I
Input
Production test pin (connected directly to GNDP in normal operation).
142
TESTMODE
I
I
Input
In normal operation this pin must be connected directly to GNDP. If it is connected to VDDP, then after RESET the
Decoder is in a test mode. This input may be changed only during RESET.
Decoder is in a test mode. This input may be changed only during RESET.
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