Sharp DV-720H (serv.man19) Service Manual ▷ View online
21
DV-720S/DV-720S(K)
DV-720H
DV-720H
10-4. IC404, IC502 IX1717GE 4M EDO DRAM
Terminal
Terminal name
Function
16-19, 22-26
A
0
-A
8
Address inputs.
14
RAS
Row address strobe.
28
UCAS
Column address strobe/upper byte control.
29
LCAS
Column address strobe/lower byte control.
13
WE
Write enable
27
OE
Output enable.
2-5, 7-10
DQ
1
-DQ
16
Data inputs/outputs.
31-34, 36-39
1, 6, 20
V
CC
+3.3V power supply.
21, 35, 40
V
SS
0V supply.
11-12, 15, 30
NC
No connection.
• Block Diagram
RAS clock
generator
CAS clock
generator
WE clock
generator
Data I/O Bus
Column decoders
Sense amplifiers
Refresh
counter
Address buffers
and predecoders
Row
decoders
Memory
array
OE clock
generator
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O
Buffer
9
Y
0
-Y
8
X
0
-X
8
512
512 16
OE
WE
UCAS
LCAS
RAS
V
CC
V
SS
A0
A1
A1
A7
A8
A8
DV-720S/DV-720S(K)
DV-720H
DV-720H
22
10-5. IC501 IX1689GE
FLASH MEMORY
Pin No.
Symbol
Type
Name and function
Byte selection address: When the device is in the x8 mode, the low or high order byte is
45
DQ
15
/A
-1
Input
selected. It is not used in the x16 mode.
(If BYTE# is high, DQ
(If BYTE# is high, DQ
15
/A
-1
input circuit does not operate.)
25-18, 8-4
A
0
-A
12
Input
Word selection address: Selection of one word of 16k byte block. These addresses are
latched during data wiring operation.
latched during data wiring operation.
3-1, 48,
A
13
-A
18
Input
Block selection address: Selection of 1/32 erase block. These addresses are latched
16, 17
during data writing, erasing and lock block operation.
29, 31, 33,
Low order byte data input/output: Command user interface writing cycle data and command
35, 38, 40,
DQ
0
-DQ
7
Input/Output input. Various data read memory identifier and status data output Chip nonselection or
42, 44
output disable: Float state
30, 32, 34, 36,
DQ
8
-DQ
14
Input/Output
High order byte data input/output: The function is the same as that of low order byte
39, 41, 43, 45
data input/output. Operative only in x16 mode. x8 mode: Float state DQ
14
/A
-1
is address.
26
CE#
Input
Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Chip becomes active only when CE# is “Low”.
Reset/Power down: If RP# is set to “Low”, the control circuit is initialized when power
is turned on. Hence, the RP#pin is set to “Low”. When power is turned on or off or in
Chip becomes active only when CE# is “Low”.
Reset/Power down: If RP# is set to “Low”, the control circuit is initialized when power
is turned on. Hence, the RP#pin is set to “Low”. When power is turned on or off or in
12
RP#
Input
case of fluctuation it is kept at “Low” so as to protect data from noise. When RP# is in
“Low” state, the device is in deep power down state. 480 ns is required to recover
from the deep power down state. If the RP# pin becomes “Low”, the whole chip operation is
interrupted and reset. After recovery the device is set to array read state.
“Low” state, the device is in deep power down state. 480 ns is required to recover
from the deep power down state. If the RP# pin becomes “Low”, the whole chip operation is
interrupted and reset. After recovery the device is set to array read state.
28
OE#
Input
Output enable: When OE# is set to “Low”, data is output from the DQ pin. When OE# is
set to “High”, the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is
set to “High”, the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is
11
WR#
Input
controlled. In “Low” state WR# becomes active. At rise edge the address and data are
fetched.
Write protection: Blanking/writing to the boot block area is input of prohibition control.
fetched.
Write protection: Blanking/writing to the boot block area is input of prohibition control.
14
WP#
Input
Blanking to the boot block area and writing actuation can't be executed at the time of
WP#=V
WP#=V
IL
.
Ready/busy: The state of internal write state machine is output. In “Low” state it is
15
RY/BY#
Output
indicated that the write state machine is in operation. If the write state machine waits for
next operation instruction, erase is suspended or it is in deep power down state, the RY/BY#
pin is in float state.
Byte enable: When BYTE# is set to “Low”, the device is set to the x8 mode. At this time
next operation instruction, erase is suspended or it is in deep power down state, the RY/BY#
pin is in float state.
Byte enable: When BYTE# is set to “Low”, the device is set to the x8 mode. At this time
47
BYTE#
Input
the DQ
8
-DQ
15
pin becomes float state. Address A
-1
selects high order/low order byte.
When BYTE# is “High”, the device is set to the x16 mode. The A
-1
input circuit is disabled.
13
Vpp
———
Write/erase power supply: 5.0
±
0.5V is applied during writing/erasing.
37
Vcc
———
Device power supply: 5.0
±
0.5V
27, 46
GND
———
Ground
9, 10
NC
———
Nonconnection
ID
Register
CSR
DQ
8-15
DQ
0-7
OUTPUT MULTIPLEXER
Program Erase
Voltage Switch
BYTE#
CUI
WSM
16-KBYTE
Block 31
16-KBYTE
Block 30
16-KBYTE
Block 1
16-KBYTE
Block 0
CE#
OE#
WE#
RP#
RY/BY#
V
PP
V
CC
GND
Y GATING/SENSING
X-DECODER
Y-DECODER
ADDRESS
COUNTER
COUNTER
A
-1.0~17
Output
Buffer
Output
Buffer
Input
Buffer
DATA
QUEUE
REGISTER
Register
Data
Comparator
ESRs
Input
Buffer
I/O Logic
Input
Buffer
ADDRESS
QUEUE
LATCHES
• Block Diagram
23
DV-720S/DV-720S(K)
DV-720H
DV-720H
10-6. IC504 IX1687GE
MICRO COM.
MD
2
V
cc
V
cc
V
cc
V
cc
V
cc
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
PD
7
/D
15
PD
6
/D
14
PD
5
/D
13
PD
4
/D
12
PD
3
/D
11
PD
2
/D
10
PD
1
/D
9
PD
0
/D
8
PE
7
/D
7
PE
6
/D
6
PE
5
/D
5
PE
4
/D
4
PE
3
/D
3
PE
2
/D
2
PE
1
/D
1
PE
0
/D
0
PA
7
/A
23
/IRQ7
PA
6
/A
22
/IRQ6
MD
1
MD
0
PF
7
/ø
PF
6
/AS
PF
5
/RD
PF
4
/HWR
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
XTAL
STBY
RES
WDTOVF
NMI
PF
3
/LWR
PF
1
/BACK
PF
0
/BREQ
PG
4
/CS0
PG
3
/CS1
PG
2
/CS2
PG
1
/CS3
PG
0
/CAS
P6
7
/CS7/IRQ3
P6
6
/CS6/IRQ2
P6
5
/IRQ1
P6
4
/IRQ0
P6
3
/TEND1
P6
2
/DREQ1
P6
1
/TEND0/CS5
P6
0
/DREQ0/CS4
PF
2
/LCAS/WAIT/BFEQO
P1
0
/PO8/TIOCA0/DACK0
P1
1
/PO9/TIOCB0/DACK1
P1
2
/PO10/TIOCC0/TCLKA
P1
3
/PO11/TIOCD0/TCLKB
P1
4
/PO12/TIOCA1
P1
5
/PO13/TIOCB1/TCLKC
P1
6
/PO14/TIOCA2
P1
7
/PO15/TIOCB2/TCLKD
P2
0
/PO0/TIOCA3
P2
1
/PO1/TIOCB3
P2
2
/PO2/TIOCC3
P2
3
/PO3/TIOCD3
P2
4
/PO4/TIOCA4
P2
5
/PO5/TIOCB4
P2
6
/PO6/TIOCA5
P2
7
/PO7/TIOCB5
P4
7
/AN7/DA1
P4
6
/AN6/DA0
P4
5
/AN5
P4
4
/AN4
P4
3
/AN3
P4
2
/AN2
P4
1
/AN1
P4
0
/AN0
V
ref
AV
cc
AV
ss
PA
5
/A
21
/IRQ5
PA
4
/A
20
/IRQ4
PA
3
/A
19
PA
2
/A
18
PA
1
/A
17
PA
0
/A
16
PB
7
/A
15
PB
6
/A
14
PB
5
/A
13
PB
4
/A
12
PB
3
/A
11
PB
2
/A
10
PB
1
/A
9
PB
0
/A
8
PC
7
/A
7
PC
6
/A
6
PC
5
/A
5
PC
4
/A
4
PC
3
/A
3
PC
2
/A
2
PC
1
/A
1
PC
0
/A
0
P3
5
/SCK1
P3
4
/SCK0
P3
3
/RxD1
P3
2
/RxD0
P3
1
/TxD1
P3
0
/TxD0
P5
0
P5
1
P5
2
P5
3
/ADTRG
ROM *
RAM
TPU
PPG
SCI
WDT
DMAC
DTC
H8S/2000 CPU
D/A converter
A/D converter
Clock oscillator
Interruption
controller
Bass Controller
Port D
Port F
Port G
Port 6
Port 5
Port 3
Port C
Port B
Port A
Port E
Port 1
Port 2
Port 4
Internal data bus
Peripheral data bus
Peripheral address bus
Internal address bus
DV-720S/DV-720S(K)
DV-720H
DV-720H
24
10-7. IC601 IX1691GE
AV DECODER
Reset, Standby and Idle Status Interface (3 pins)
Pin No.
Pin name
Type
Direction
Function
137
RESET#
I
I
Input
Reset input. Once de-asserted, the Decoder starts the initialization process.
136
STNBY#
I
I
Input
Stand-by input. When asserted together with RESET#, all outputs and bidirectional pins float, such that the Decoder
is electrically disconnected from its surroundings. All internal clocks are disabled, and the power consumption is
minimized.
is electrically disconnected from its surroundings. All internal clocks are disabled, and the power consumption is
minimized.
174
IDLE
3-S
O (p.u.)
Reset: output (high)
Standby: 3-S (p.u.)
Standby: 3-S (p.u.)
Idle, Init and Reset states indication output.
Host Interface (29 pins)
Pin No.
Pin name
Type
Direction
Function
176
HWID
I
I
Input
Determines the width of the host interface data bus. It is allowed to be changed only during RESET.
A low level (GNDP) configures the Decoder to 2- or 8-bit host data interface, a high level (VDDP) to 16-bit width.
A low level (GNDP) configures the Decoder to 2- or 8-bit host data interface, a high level (VDDP) to 16-bit width.
175
HORD
I
I
Input
Determines the order of bytes on the host interface data bus in case of 16-bit width (HWID at VDDP). It is allowed to
be changed only during RESET. A low level (GNDP) configures the Decoder to input/output the m.s. byte on
HD[15:8], a high level (VDDP)to input/output the m.s. byte on HD[7:0]. If HWID is at GNDP level, this input is use to
select between the 2-bits mode (VDDP) and 8-bits mode (GNDP)
be changed only during RESET. A low level (GNDP) configures the Decoder to input/output the m.s. byte on
HD[15:8], a high level (VDDP)to input/output the m.s. byte on HD[7:0]. If HWID is at GNDP level, this input is use to
select between the 2-bits mode (VDDP) and 8-bits mode (GNDP)
2
HTYPE
I
I
Input
Determines the protocol type for the 8 and 16 bits modes host interface. It is allowed to be changed only during
RESET. A low level (GNDP) configures the Decoder to type A, a high level (VDDP) to type B.
RESET. A low level (GNDP) configures the Decoder to type A, a high level (VDDP) to type B.
15
HD[7]
3-S
I/O (r.t.)
Reset: input (p.d.)
16
HD[6]
3-S
I/O (r.t.)
Standby: 3-S (p.d.)
17
HD[5]
3-S
I/O (r.t.)
18
HD[4]
3-S
I/O (r.t.)
19
HD[3] —HVCTL
3-S
I/O (p.u.)
20
HD[2] —HVAD[1]
3-S
I/O (r.t.)
21
HD[1] —HVAD[2]
3-S
I/O (r.t.)
22
HD[0] —HVCLK
3-S
I/O (p.u.)
For 16 bits mode, the 8 l.s. data lines of host data bus. For 8 bits mode, only these signals are defined as host data
signals. For 2 bits mode only 4 lines are used:
HVCTL—Host VIP mode control signal
HVAD[1:0]—Host VIP mode address/data bus
HVCLK— Host VIP mode clock.
signals. For 2 bits mode only 4 lines are used:
HVCTL—Host VIP mode control signal
HVAD[1:0]—Host VIP mode address/data bus
HVCLK— Host VIP mode clock.
7
HD[11]
3-S
I/O (p.d.)
Reset: input (p.d.)
9
HD[10]
I/O (r.t.)
Standby: 3-S (p.d.)
11
HD[9]
I/O (r.t.)
13
HD[8]
I/O (r.t.)
When HWID is connected to VDDP, these are data lines 11:8 of the 16-bit host data bus.
3
HD[15]
3-S
I/O (r.t.)
Reset: input (p.d.)
4
HD[14]
I/O (r.t.)
Standby: 3-S (p.d.)
5
HD[13]
I/O (r.t.)
6
HD[12]
I/O (r.t.)
When HWID is connected to VDDP, these are data lines 15:12 of the 16-bit host data bus. When HWID is connected
to GNDP, these are the CD-DSP I
to GNDP, these are the CD-DSP I
2
S input port pins, as explained in the CD-DSP pin description.
24
HA[3]
I
I
Input
25
HA[2]
I
I
26
HA[1]
I
I
27
HA[0]
I
I
Host address inputs. These input signals indicate the register accessed in every cycle on the host interface.
29
HCS#
I
I
Input
Host chip-select input.
28
HWR#—HR/W#
I
I
Input
In host protocol type A (HTYPE=GNDP):HR/W#. This input determines the direction of the host access.
In host protocol type B (HTYPE=VDDP):HWR#. Host write input.
In host protocol type B (HTYPE=VDDP):HWR#. Host write input.
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