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Pin No.

Pin name

Type

Direction

Function

124

ICEMODE#

I

I

Input

In normal operation this pin must be connected directly to VDDP. If it is asserted, then the ADP goes into ICE mode.
In this mode 4 of the Decoder pins turn into ICE interface pins:
HD[7]=TMS—ICE interface mode select input
HD[6]=TDI—ICE interface data input
HD[5]=TDO—ICE interface data output
HD[4]=TCK—ICE interface clock

Power Signals (51 pins)

Pin No.

Pin name

Type

Direction

Function

*

GNDP

(* pins 8, 37, 46, 53, 62, 66, 77, 83, 97, 109, 141, 173)

Digital ground of 3.3 V supply.

*

VDDP

(* pins 1, 14, 23, 35, 41, 49, 55, 64, 68, 74, 80, 86, 94, 102, 111, 139,
148, 160)

3.3 V Digital power supply.

145

GNDP-A2
Digital ground of filtered 3.3 V supply for AMCLK.

143

VDDP-A2
3.3 V filtered digital power supply for AMCLK.

*

GNDC

(* pins 12, 32, 70, 104, 126, 165)

Digital ground of 2.5 V supply.

*

VDDC

(* pins 10, 30, 60, 106, 128, 163)

2.5 V Digital power supply.

135

GNDA
Ground plane of internal PLL circuit.

133

VDDA
2.5 V Power supply for internal PLL circuit.

116

VDD_DAC
2.5 V Analog power supply for the DACs.

113

GND_DACD

119

GND_DACB

121

GND_DACP

122

GND_DACS
Grounds for the DACs 2.5 V analog power supply

DVP

Demux/Video

Processor

Coded
Subpicture

Decoded
Pictures

OSD
Data

Coded
Audio

Closed

Caption

Modulator

Video

Processing

Unit

On-Screen

Display

Processor

ADP

Audio Decoder/

Processor

Subpicture

Decoder

and

Highlight

Processor

CSS

Decryption

DVD-DSP.
CD-DSP
or Host Bus

Host Interface

ZR36730

System

Clock

(SCLK)

8-bit YUV
Analog video output

2-Channel

Digital

Audio In

2-8 channels of digital audio out
plus S/PDIF out
(optionally configurable as 4-ch.
Dolby   ProLogic

TM

 or 6-8 ch. surround

              simulation, etc., depending
              on optional audio
              post-processing)

R

16 MBit SDRAM

•    Coded video, audio, subpictures, and navigation (NV_PCK)

•    Decoded pictures

•    OSD Data

Coded Video, Audio, 

Subpictues and NV_PCK

Coded Video

Decoded Pictures

35

CLK

Clock

The system clock input. All other inputs are referenced to the SDRAM on
the rising edge of CLK.

34

CKE

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh.

18

CS

Chip Select

Command input enable or mask except CLK, CKE and DQM

19

BS

Bank Address

Select either one of banks during both RAS and CAS activity.

20~24

A0~A10

Address

Row Address: RA0~RA10, Column Address: CA0~CA7

27~32

Auto-precharge flag:A10

17, 16, 15

RAS, CAS, WE

Row Address Strobe,

RAS, CAS and WE define the operation.

Column Address Strobe,

Refer function truth table for details.

Write Enable

14, 36

DOML, DOMU

Data Input/Output Mask

DOM control output buffer in read mode and mask input data in write mode.

2, 3, 5,

I/O0~15

Data Input/Output

Multiplexed data input/output pin

 6, 8, 9, 11, 12, 39, 40,
 42, 43, 45, 46, 48, 49

VCC/VSS

Power Supply/Ground

Power supply for internal circuit and input buffer.

 1, 25, 26

4, 7, 10,

VCCO/VSSO

Data Output Power/Ground Power supply for DO

 13, 38, 41, 44, 47, 50

33, 37

NC

No Connection

No connection

Terminal

Terminal Name

Name

Input Function

Refresh

Interval Timer

Refresh

Counter

Self Refresh Counter

Address
Register

Burst Length

Counter

Column Addr.

Latch & Counter

512Kx16

Bank 1

Column Decoder

Sense AMP & I/O gates

Column Decoder

Sense AMP & I/O gates

Mode Register

Test Mode

I/O Control

512Kx16

Bank 0

Row Addr. Latch/Predecode

Row Addr. Latch/Predecode

State Machine

Data Input/Output Buffers

Row Decoder

Precharge

Row Active

Column Active

Overflow

Address[0:10]

Audio/Self Refresh

Ref. Addr.[0:11]

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

CLK

CKE

BS(A11)

CS

RAS

CAS

WE

DOMU

DOML

Pin No.

Terminal name

Operation function

Pin No. Terminal name

Operation function

1

FWD

Loading driver FWD input terminal

15

VO4(+)

Driver CH4   Negative output

2

OPIN1(+)

CH1 Former stage amplifier nonreverse input terminal

16

VO4(-)

Driver CH4   Positive output

3

OPIN1(-)

CH1 Former stage amplifier reverse input terminal

17

VO3(-)

Driver CH3   Positive output

4

OPOUT1

CH1 Former stage amplifier output terminal

18

VO3(+)

Driver CH3   Negative output

5

OPIN2(+)

CH2 Former stage amplifier nonreverse input terminal

19

GND

Ground terminal

6

OPIN2(-)

CH2 Former stage amplifier reverse input terminal

20

BIAS

Bias input terminal

7

OPOUT2

CH2 Former stage amplifier output terminal

21

MUTE

Mute control terminal

8

VCC

Power terminal

22

OPOUT3

CH3 Former stage amplifier output terminal

9

VOL(-)

Loading driver  Negative output

23

OPIN3(-)

CH3 Former stage amplifier reverse input terminal

10

VOL(+)

Loading driver  Positive output

24

OPIN3(+)

CH3 Former stage amplifier nonreverse input terminal

11

VO2(-)

Driver CH2   Negative output

25

OPOUT4

CH4 Former stage amplifier output terminal

12

VO2(+)

Driver CH2   Positive output

26

OPIN4(-)

CH4 Former stage amplifier reverse input terminal

13

VO1(-)

Driver CH1   Negative output

27

OPIN4(+)

CH4 Former stage amplifier nonreverse input terminal

14

VO1(+)

Driver CH1   Positive output

28

REV

Loading driver REV input terminal

Note 1: Positive and negative output the driver have polarity with respect to input. (An example: 4 pin terminal voltage

‘HIGH’: 14 pin terminal voltage ‘HIGH’)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

-

+

-

+

10K

10K

16K

16K

-

+

-

+

10K

16K

10K

16K

MUTE

REV    OUTF
FWD   OUTR

Loading Driver

VCC

10K

10K

10K

10K

10K

10K

10K

10K

-       +

Level

Shift

-       +

Level

Shift

10K

10K

10K

10K

10K

10K

10K

10K

-       +

Level

Shift

-       +

Level

Shift

+ -

+ -

- +

- +

-+

-+

- +

- +

-+

-+

+ -

+ -

Pin No.

Terminal name

I/O

Operation function

1-4

SW1 to SW4

I

General purpose input pins

5

DOUT

O

Data output pin (N-Channel, Open-Drain)
This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit).

6

DIN

I

Data input pin
This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit)

7, 43

GND

–

Ground pin

8

CLK

I

Clock input pin
This pin reads serial data at the rising edge and outputs data at the falling edge.

9

STB

I

Serial interface strobe pin
The data input after the STB has fallen is processed as a command.
When this pin is "HIGH", CLK is ignored.

10-13

K1 to K4

I

Key data input pins
The data inputted to these pins are latched at the end of the display cycle.

14, 38

VDD

–

Logic power supply

15-20

SG1/KS1 to

O

High-voltage segment output pins also acts as the key source

SG6/KS6

21-25

SG7 to SG11

O

High voltage segment output pin

26, 28-31

SG12/GR11

High voltage segment/grid output pins

SG13/GR10 to

O

SG16/GR7

27

VEE

–

Pull-down level

32-37

GR6 to GR1

O

High-voltage grid output pins

42-39

LED1 to LED4

O

LED output pin

44

OSC

I

Osillator input pin
A resistor is connected to this pin to determine the oscillation frequency.

Serial

Data

Interface

Control

Segment

Driver/

Grid

Driver/

Key Scan

Output

Grid

Driver

Dimming Circuit

Timing Generator

Key Matrix Memory

Display Memory

(16bits x 11 Words)

OSC

General

Input

Register

LED

Driver

10 11 12 13

14, 38 7, 43

27

VDD

GND

VEE

K1 K2 K3 K4

SW1

SW2

SW3

SW4

LED1

LED2

LED3

LED4

1

6

5

8

9

42

41

40

39

2

3

4

OSC

VDD

R

DIN

DOUT

CLK

STB

44

15

16

17

18

19

20

21

22

23

24

25

26

28

29

30

31

37
36
35

34

33
32

GR1

GR2

GR3

GR4

GR5

GR6

SG12/GR11

SG13/GR10

SG14/GR9

SG15/GR8

SG16/GR7

SG1/KS1

SG2/KS2

SG3/KS3

SG4/KS4

SG5/KS5

SG6/KS6

SG7

SG8

SG9

SG10

SG11