DOWNLOAD Sharp DV-660H (serv.man2) Service Manual ↓ Size: 1.96 MB | Pages: 51 in PDF or view online for FREE

Pin No.

Pin name

Type

Direction

Function

Address bus output for SDRAM connection.

Tip select output for SDRAM connection.
Tip select output terminal for SDRAM connection. It is connected to 2nd
SDRAM.
RAS output terminal for SDRAM connection.
Clock output terminal for SDRAM connection.
CAS output terminal for SDRAM connection.
Write enable output terminal for SDRAM.
Data masking output terminal for SDRAM.

Bi-directional data bus for SDRAM.

Function

Data error input for DVD-DSP connection.
Sector start input for DVD-DSP connection.
Data valid input for DVD-DSP connection.
Data strobe input for DVD-DSP connection.
Data request output for DVD-DSP connection.

Stream input for DVD-DSP connection

Pin No.

Pin name

Type

Direction

143

DVDERR

I

I

144

DVDSOS

I

I

146

DVDVALID

I

I

147

DVDSTRB

I

I

148

DVDREQ

O

O

149

151-154 DVDDAT[7:0]

I

I

156-158

DVD-DSP interface terminal list

DVD-DSP interface

Pin No.

Pin name

Type

Direction

38-39
42-47

RAMADD[11:0]

O

O

49-52

54

RAMCS0#

O

O

55

RAMCS1#

O

O

56

RAMRAS#

O

O

57

PCLK

O

O

59

RAMCAS#

O

O

60

RAMWE#

O

O

61

RAMDQM

O

O

62

64-67
69-72

RAMDAT[15:0]

3-S

I/O

74-79

82

SD-RAM interface terminal list

SDRAM interface

Power terminal · other list

Pin No.

Pin name

Type

Direction

1, 13, 23

40, 41
53, 68
80, 81

GND

93, 108

120, 121
125, 131
145, 160
8, 18, 28

33, 48
58, 63
73, 86

VDD

98, 103

113, 133

140,

150, 155

83

TESTMODE

I

I

127

SCNENBL

I

I

130

PWRDN#

I

I

134

PLLGND

138

PLLVDD

139

ICEMODE

I

I

Pin No.

Pin name

Type

Direction

Function

Ground terminal

+ 3.3V power input terminal

Test terminal. Pull it down to GND.
Test terminal. Pull it up to VDD.
Power-down terminal. When it is [low], current consumption becomes
minimum with all functions of the device stopped. (Power-down mode) To
return it to normal state, set the terminal at [high]. Then, reset the device
with RESET# terminal.
Ground terminal for internal PLL.
Internal PLL + 3.3V power input terminal.
Test terminal. Pull it down to GND.

Power terminal · other

35

CLK

System Clock

Active on the positive going edge to sample all inputs.

18

CS

Chip Select

Disables or enables device operation by masking or enabling all inputs
except CLK. CKE and L(U)DQM

34

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in stanby.

21~24

A0~A10/AP

Address

Row/column address are multiplexed on the same pins.

27~32

Row address: RA0~RA10, column address: CA0~CA7

20
19

BA

Bank Select Address

Selects bank to be activated during row address latch time.
Selects bank for read/write during clumn address latch time.

17

RAS

Row Address Strobe

Latches row address on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

16

CAS

Column Address Strobe

Latches addresses on the positive going edge of the CLK with CAS low.
Enables row access.

15

WE

Write Enable

Enable write operation and row precharge.
Latches data in starting from CAS, WE active.

1, 36

L(U)DQM

Data Input/Output Mask

Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.

2, 3, 5,

DQ0~15

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

 6, 8, 9, 11, 12, 39, 40,
 42, 43, 45, 46, 48, 49

V

DD

/Vss

Power Supply/Ground

Power and ground for the input buffers and the core logic.

 25, 1/26, 50

V

DD

/VssQ

Data Output Power/Ground Isolated power supply and ground for the output buffers to provide

44, 38, 13, 7/4, 10, 41, 47

improved noise immunity.

37

NC/RFU

No Connection/

This pin is recommanded to be left No Connection on the device

Reserved for Future Use

Terminal

Terminal Name

Name

Input Function

CLK

CLK

CKE

CS

RAS

CAS

WE

ADD

LCKE

Address Register

Bank Select

Row Buffer

Refrsh Counter

Rown Decorder

Col. Buffer

LRAS

LRAS

LCBR

LCBR

LWE

LCAS

L(U)QCM

Timing Register

LWCBR

LDQM

Programming Resiter

Latency & Burst Length

Column Decoder

Data Input Register

512K x 16

512K x 16

Sense AMP

I/O Control

Output Buffer

LWE

LDQM

DQi

• Samsung Electronics reserves the right to
  change products or specification without 

T.S.D ; Thermal shutdown

D; Drive buffer

Unit of resistance is [

Ω

].

CTL1

CTL2

CH1

CH2

CH3

CH4

CH5

L

L

OFF

ON

L

H

H

L

ON

OFF

H

H

OFF

ON

OFF

ON

CTL1 and CTL2

Note: OFF state: Output has high impedance.

For F and R (CH5 control, valid only when CH5 is ON)

F

R

Output mode

L

L

High impedance

L

H

Reversing (reverse)

H

L

Forward rotation (forward)

H

H

Brake

Pin No.

Terminal name

Operation function

Pin No. Terminal name

Operation function

1

OPOUT

Ope amp. output terminal

15

CH2-OUT-

CH2 Negative output terminal

2

CH4-IN

CH4 Input terminal 16

CH2-OUT+

CH2 Positive output terminal

3

CH4-IN’

CH4 Gain adjustment input terminal

17

CH1-OUT-

CH1 Negative output terminal

4

CTL1

Contorol 1 input terminal

18

CH1-OUT+

CH1 Positive output terminal

5

CTL2

Contorol 2 input terminal

19

CH1-IN

CH1 Input terminal

6

FWD

Tray forward input terminal

20

CH1-IN’

CH1 Input terminal for gain adjustment

7

REV

Tray reverse input terminal

21

VCC

VCC

8

TRAY-IN

Tray input terminal 22

CH2-IN

CH2 Input terminal

9

GND

Sub-straight GND

23

CH2-IN’

CH2 Input terminal for gain adjustment

10

CH5-OUT-

Tray negative output terminal

24

CH3-IN

CH3 Input terminal

11

COM-OUT

Tray positive output terminal/CH4

25

CH3-IN’

CH3 Input terminal for gain adjustment

negative output terminal

12

CH4-OUT+

CH4 Positive output terminal

26

VREF-IN

Bias amp. input terminal

13

CH3-OUT+

CH3 Positive output terminal

27

OPIN+

Operational amplifier nonreverse input terminal

14

CH3-OUT-

CH3 Negative output terminal

28

OPIN-

Operational amplifier reverse input terminal

Note 1: Positive and negative output have polarity with respect to input. (An example: 19 pin input ‘H’: 18 pin output  ‘H’)

Note 2: Tray positive output and tray negative output have polarity with respect to mode. (An example: 11 pin output

‘H’ in FORWARD mode)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CH2-OUT

CH1-OUT

CH1-IN

CH2-IN

CH3-IN

10K

10K

13.3K

13.3K

13.3K

10K

+

-

Level shift

Level shift

Level shift

Level shift

VCC

D

D

D

D

D

D

D

D

D

V/I

T.S.D

26.6K

10K

CTL1

CTL2

PWD

REV

LOGIC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

CH4-IN

CH5-IN

CH5-OUTCH4-OUT CH3-OUT

+

-

+

-

+

-

+

-

Pin No.

Terminal name

I/O

Operation function

Remarks

1

VSS

–

Digital ground terminal.

2

BCK

O

Bit clock (1.4122MHz) output terminal.

3

AOUT

O

Audio data output terminal.

4

DOUT

O

Digital out output terminal.

5

MBOV

O

Buffer memory over signal output terminal. Over: “H”

6

IPF

O

Correction flag output terminal. When correction disable symbol
is given if AOUT output is C2 correction: “H”.

7

SBOK

O

Sub-code Q data CRCC judgment result output terminal.
Judgment result OK: “H”.

8

CLCK

I/O

Sub-code P to W data read clock output/input terminal.
Selectable with command bit.

9

VDD

–

Digital + power terminal

10

VSS

–

Digital ground terminal

11

DATA

O

Sub code P-W data output terminal.

12

SFSY

O

Playback system frame sync signal output terminal.

13

SBSY

O

Subcode block sync output terminal.
When subcode sync is detected, S1 position: “H”.

14

SPCK

O

Processor status signal read clock (176.4 kHz) output terminal.

15

SPDA

O

Processor status signal output terminal.

16

COFS

O

Correction system frame clock (7.35 kHz) output terminal.

17

MONIT

O

LSI internal signal monitor terminal.
DSP internal flag and PLL system clock can be monitored with
microcomputer command.

18

VDD

–

Digital + power terminal.

19

TESIO0

I

Test input/output terminal. Usually fixed to “L”.

20

P2VREF

–

PLL system 2VREF terminal.

21

SPDO

O

VCO center frequency shift terminal.

22

PDOS

O

EFM and PLCK signal phase error signal output terminal.
 (To be used when x8 speed operation is used)

23

PDO

O

EFM and PLCK signal phase error signal output terminal.

24

TMAXS

O

TMAX detection result output terminal.
To be selected with command bit TMPS.

25

TMAX

O

26

LPFN

I

Reverse input terminal for low pass filter amplifier.

27

LPFO

O

Output terminal for low pass filter amplifier.

28

PVREF

–

PLL system VREF terminal.

29

VCOREF

I

VCO center frequency reference level terminal.
To be fixed usually to “PVREF”.

30

VCOF

O

Filter terminal for VCO.

31

AVSS

–

Analog system ground terminal.

32

SLCO

O

Data slice level generation DAC output terminal.

33

RFI

I

RF signal input terminal.

34

AVDD

–

Analog system power terminal.

35

RFCT

I

RFRP signal center level input terminal.

36

RFZI

I

RFRP zero cross input terminal.

37

RFRP

I

RF ripple signal input terminal.

38

FEI

I

Focus error signal input terminal.

39

SBAD

I

Sub-beam addition signal input terminal.

40

TSIN

I

Test input terminal. To be fixed usually to “Vref”

41

TEI

I

Tracking error signal input terminal.
(Fetching when tracking servo is ON)

42

TEZI

I

Tracking error zero cross input terminal.

43

FOO

O

Focus equalizer output terminal.

TMAX detection result

TMAXoutput

Longer than specific period

“P2VREFF”

Shorter than specific period

“VSS”

Within specified period

“HiZ”