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41

RFA

O

RF total addition output

2.2[V]

42

EQB

I

Boost adjustment

VrD

When EQB is raised, the boost increases.

43

EQF

I

Frequency adjustment

VrD

When EQF is raised, shift to the
high frequency side occurs.

44

MDI1

I

Monitor input

–

45

LDO1

O

Drive output

–

46

P1TN

I

TE–input (DVD)

VrA

47

P1TP

I

TE+input (DVD)

VrA

48

NC

–

NC terminal

–

To be connected to GND

49

P1FN

I

FE–input (DVD)

VrA

50

P1TP

I

FE+input (DVD)

VrA

51

LDP1

I

APC polarity 1

–

Positive polarity when this terminal
is connected to Vcc.

52

P1DI

I

D input (DVD)

53

P1CI

I

C input (DVD)

VrA

54

P1BI

I

B input (DVD)

VrA

55

P1AI

I

A input (DVD)

VrA

56

GNDR

–

GND terminal (RF)

–

57

LDP2

I

APC polarity 2

–

Positive polarity when this terminal
is connected to Vcc.

58

P2AI

I

A input (CD)

VrA

59

P2BI

I

B input (CD)

VrA

60

P2CI

I

C input (CD)

VrA

61

P2DI

I

D input (CD)

VrA

62

GNDS

–

GND terminal (Servo)

–

63

P2FP

I

FE+input (CD)

VrA

64

P2FN

I

FE–input (CD)

VrA

Pin No. Terminal name

I/O

Operation function

Terminal DC Voltage(TYP.)

Remarks

Terminal

Terminal name

Function

10~13,16~20,9

A0~A8,A9R

Address input

8

RAS

Row address strobe

23

CAS

Column address strobe

1~5,24~27

DQ1~DQ8

Data input/Data output

22

OE

Output enable

7

WE

Light enable

1

Vcc

Power (5V)

28

Vss

Ground (0V)

21

NC

Not connected

P1FN

P1FP

LDP1

P1DI

P1CI

P1BI

P1AI

GNDR

LDP2

P2AI

P2BI

P2CI

P2DI

GNDS

P2FP

P2FN

DPDB

VccR

NC

NC

RFO

RPP

RPB

RPO

RPZ

VccS

DFTN

FEO

TEO

LVL

LccP

VCKF

NC

P1TP

P1TN

LDO1

MDI1

EQF

EQB

RFA

RFDC

GND2

EQD

NC

Vcc2

PSC

FEB

TEB

GND

P2TP

P2TN

LDO2

MDI2

VrA

VrD

Vdd

DPAC

DPBD

DPD1

DPD2

SCB

SCL

SCD

SRCK

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

APC1

sel-RF

R-gain

Adjust

EQ

F-gain
Adjust

F-gain
Adjust

RF Ripple

creation

FE creation

DPDTE

creation

FE-gain

Adjust

TE-gain

Adjust

Level detect

T-gain
Adjust

3BTE creation

APC2

B U S

Time

constant 

adjustment

sel-PD

sel-PD

sel-PD

mode-TE

sel-FE

sel-IC

sel-TE

sel-DPD

sel-LVL

Pin No.

Terminal name

I/O

Operation function

Remarks

1

DPCK1

I

Signal processing reference clock input.

0.5-3.3Vp-p Feedback
resistor built in.

2

DVDD3

–

Digital power. (3.3V)

For logic cell

3

SVCK1

I

Servo reference clock input. (Oscillation circuit input terminal)

3.3V-I/F Feedback

4

SVCK0

O

Servo reference clock output. (Oscillation circuit input terminal)

resistor built in.

5

DVSS

–

Digital power. (0V)

For logic cell

6

DVDD2

–

Digital power. (3.3V)

For logic cell

7

N.C.

–

User use prohibited.

Open

8

HDWT

I

MPU write signal.

TTL level

9

HDRD

I

MPU read signal.

TTL level

10

HCEN

I

MPU chip selection.

TTL level

11

HD0

I/O

MPU data bus.

TTL level

12

HD1

I/O

MPU data bus.

TTL level

13

HD2

I/O

MPU data bus.

TTL level

14

HD3

I/O

MPU data bus.

TTL level

15

HD4

I/O

MPU data bus.

TTL level

16

HD5

I/O

MPU data bus.

TTL level

17

HD6

I/O

MPU data bus.

TTL level

18

HD7

I/O

MPU data bus.

TTL level

19

DVSS

–

Digital power. (0V)

For I/O cell

20

DVDD5

–

Digital power. (5V)

For I/O cell

21

HINT

O

MPU interruption signal. (Occurrence of interruption = “L”)

OPEN DRAIN

22

HA0

I

MPU address bus.

TTL level

23

HA1

I

MPU address bus.

TTL level

24

PLCK

I/O

Read channel clock input/output terminal.

25

ED0

–

User use is prohibited (N.C.) since it is for shipping adjustment.

Open

26

ED1

–

27

ED2

–

28

ED3

–

29

ED4

–

30

ED5

–

31

ED6

–

32

ED7

–

33

TEST

I

For shipping adjustment.

Set to “L”

34

PDON

O

PLL phase error signal output. (Negative polarity)

35

PDOP

O

PLL phase error signal output. (Positive polarity)

36

RLLD

O

RLL detection result output.

37

LPFN

I

PLL loop filter amp. reverse input.

38

LPFO

O

PLL loop filter amp. output.

39

VCOF

O

VCO filter terminal.

40

SLCO

O

Built-in comparator reference voltage output terminal.

41

AVSS

–

Analog power. (0V)

42

AVR

O

Non-PLL system analog reference potential. (1.65V)

43

VRC

–

Resistance division point potential. (For analog reference
potential generation: 1.65)

44

PVR

O

PLL system analog reference potential. (1.65V)

45

AVDD

–

Analog power. (3.3V)

46

RVR2

–

2nd reference voltage. (For capacitor connection)

47

RVDD

–

Exclusive-use power terminal. (3.3V)

48

RFIN

I

RF signal input.

49

RVSS

–

Exclusive-use power terminal. (0V)

50

RVR1

–

1nd reference voltage. (For capacitor connection)

51

DVR

I

DMO reference potential. (1.65V recommended)

52

DMO

O

Disc equalizer output for DVD. (Triple value PWM + HiZ)

53

RASN

O

External RAM row address selection. (Negative logic)

54

CASN

O

External RAM row address selection. (Negative logic)

Pin No.

Terminal name

I/O

Operation function

Remarks

55

MOEN

O

External RAM output permission signal.

56

MWEN

O

External RAM read/write selection.

57

DVSS

–

Digital power. (0V)

For logic cell

58

DVDD3

–

Digital power. (3.3V)

For logic cell

59

MA9

O

External RAM address bus.

60

MA8

O

External RAM address bus.

61

MA7

O

External RAM address bus.

62

MA6

O

External RAM address bus.

63

MA5

O

External RAM address bus.

64

MA4

O

External RAM address bus.

65

MA3

O

External RAM address bus.

66

MA2

O

External RAM address bus.

67

MA1

O

External RAM address bus.

68

MA0

O

External RAM address bus.

69

DVSS

–

Digital power. (0V)

For I/O cell

70

DVDD5

–

Digital power. (5V)

For I/O cell

71

MD7

I/O

External RAM data bus.

TTL level

72

MD6

I/O

External RAM data bus.

TTL level

73

MD5

I/O

External RAM data bus.

TTL level

74

MD4

I/O

External RAM data bus.

TTL level

75

MD3

I/O

External RAM data bus.

TTL level

76

MD2

I/O

External RAM data bus.

TTL level

77

MD1

I/O

External RAM data bus.

TTL level

78

MD0

I/O

External RAM data bus.

TTL level

79

SD7

O

MPEG data output.

80

SD6

O

MPEG data output.

81

SD5

O

MPEG data output.

82

SD4

O

MPEG data output.

83

DVSS

–

Digital power. (0V)

For logic cell

84

DVDD3

–

Digital power. (3.3V)

For logic cell

85

SD3

O

MPEG data output.

86

SD2

O

MPEG data output.

87

SD1

O

MPEG data output.

88

SD0

O

MPEG data output.

89

SERR

O

MPEG data reliability flag. (Data error: “L”)

90

SBGN

O

MPEG output sector sync signal. (Sector top: “L”)

91

SENB

O

MPEG data effective flag. (Effective state: “L”)

92

SDCK

O

MPEG data transfer clock.

93

DVSS

–

Digital power. (0V)

For logic cell

94

SREQ

I

MPEG data request flag. (Request state: “L”)

TTL level

95

RSTN

I

Hard reset input. (Reset state: “L”)

96

DVDD3

–

Digital power. (3.3V)

For logic cell

97

STDA

O

Operation state monitor data.

Common with PWM.

(Output synchronizing with SDCK fall)

98

STCK

O

Operation state monitor sync signal. (Data top bit: “L”)

Common with PWM.

99

UPWM

O

General-use PWM output.

4mA, 5V-I/F

100

DVSS

–

Digital power. (0V)

For logic cell

Symbol

Type

Name and function

Byte selection address: When the device is in the x8 mode, the low or high order byte is

DQ

15

/A

-1

Input

selected. It is not used in the x16 mode.
(If BYTE# is high, DQ

15

/A

-1

 input circuit does not operate.)

A

0

-A

12

Input

Word selection address: Selection of one word of 16k byte block. These addresses are
latched during data wiring operation.

A

13

-A

17

Input

Block selection address: Selection of 1/32 erase block. These addresses are latched
during data writing, erasing and lock block operation.
Low order byte data input/output: Command user interface writing cycle data and command

DQ

0

-DQ

7

Input/Output

input. Various data read memory identifier and status data output Chip nonselection or output
disable: Float state

DQ

8

-DQ

15

Input/Output

High order byte data input/output: The function is the same as that of low order byte data
input/output. Operative only in x16 mode. x8 mode: Float state DQ

15

/A

-1

 is address.

CE#

Input

Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Chip becomes active only when CE# is “Low”.
Reset/Power down: If RP# is set to “Low”, the control circuit is initialized when power is turned
on. Hence, the RP#pin is set to “Low”. When power is turned on or off or in case of fluctuation it

RP#

Input

is kept at “Low” so as to protect data from noise. When RP# is in “Low” state, the device is in
deep power down state. 480 ns is required to recover from the deep power down state. If the RP#
pin becomes “Low”, the whole chip operation is interrupted and reset. After recovery the device is set
to array read state.

OE#

Input

Output enable: When OE# is set to “Low”, data is output from the DQ pin. When OE# is
set to “High”, the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is controlled.

WE#

Input

In “Low” state WE# becomes active. At rise edge the address and data are fetched.
Ready/busy: The state of internal write state machine is output. In “Low” state it is indicated that the

RY/BY#

Output

write state machine is in operation. If the write state machine waits for next operation instruction, erase
is suspended or it is in deep power down state, the RY/BY# pin is in float state.
Byte enable: When BYTE# is set to “Low”, the device is set to the x8 mode. At this time the

BYTE#

Input

DQ

8

-DQ

15

 pin becomes float state. Address A

-1

 selects high order/low order byte.

When BYTE# is “High”, the device is set to the x16 mode. The A

-1

 input circuit is disabled.

Vpp

Write/erase power supply: 5.0 

±

 0.5V is applied during writing/erasing.

Vcc

Device power supply: 5.0 

±

 0.5V

GND

Ground

NC

Nonconnection

ID

Register

CSR

ESRs

DQ

8-15

DQ

0-7

OUTPUT MULTIPLEXER

Program Erase

Voltage Switch

BYTE#

CUI

WSM

16-KBYTE

Block 31

16-KBYTE

Block 30

16-KBYTE

Block 1

16-KBYTE

Block 0

CE#

OE#

WE#

RP#

RY/BY#

V

PP

V

CC

GND

Y GATING/SENSING

X-DECODER

Y-DECODER

Input

Buffer

ADDRESS

QUEUE

LATCHES

ADDRESS
COUNTER

A

-1.0~17

Output

Buffer

Output

Buffer

Input

Buffer

Input

Buffer

I/O Logic

DATA

QUEUE

REGISTER

Register

Data 

Comparator