Sharp DV-660H (serv.man2) Service Manual ▷ View online
DV-660S
DV-660H
DV-660H
Pin1~15 ........ There is a possibility of simultaneous change.
Operating frequency: Approx. 10 MHz
Pin18~47 ..... There is a possibility of simultaneous change.(Static signal)
Operating frequency: Approx. 1 MHz
Pin50~57 ..... There is almost no possibility of simultaneous change.
Operating frequency: Approx. 1 MHz
Pin63 ............ Not used
• Block Diagram
Data Buffer
Latch D
Data Buffer
Latch C
Data Buffer
Latch B
Data Buffer
Latch A
Data Buffer
R/W CTL
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VDD
EXPD(3)
EXPD(4)
EXPD(5)
BUFDO
BUFDI
SBUFBO
SBUFBI
SBUFAO
SBUFAI
MRST
MODE
BUFCO
TEST
BUFCI
VSS
VDD
SOUT(3)
SOUT(4)
SOUT(5)
MRST
MODE
SEL
TEST
CK
VSS
VSS
EXPD(2)
EXPD(1)
EXPD(0)
EXPC(5)
EXPC(4)
EXPC(3)
VSS
EXPC(2)
EXPC(1)
EXPC(0)
EXPBU(3)
EXPBU(2)
EXPBU(1)
EXPBU(0)
VDD
VSS
SOUT(2)
SOUT(1)
SOUT(0)
S2(5)
S2(4)
S2(3)
VSS
S2(2)
S2(1)
S2(0)
Q2(7)
Q2(6)
Q2(5)
Q2(4)
VDD
VSS
EXPBL(3)
EXPBL(2)
EXPBL(1)
EXPBL(0)
EXPAU(3)
EXPAU(2)
VDD
VSS
EXPAU(1)
EXPAU(0)
EXPAL(3)
EXPAL(2)
EXPAL(1)
EXPAL(0)
VDD
VSS
Q2(3)
Q2(2)
Q2(1)
Q2(0)
Q1(7)
Q1(6)
VDD
VSS
Q1(5)
Q1(4)
Q1(3)
Q1(2)
Q1(1)
Q1(0)
VDD
VDD
HADR0
HADR1
HADR2
HCS
HWR
HRD
HDAT0
HDAT1
HDAT2
HDAT3
HDAT4
HDAT5
HDAT6
HDAT7
VSS
VDD
D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
S1(0)
S1(1)
S1(2)
S1(3)
S1(4)
S1(5)
VSS
In/Output Pin
Exclusive-use pin
In/Output Pin
In/Output Pin
In/Output Pin
In/Output Pin
Output:
Open drain
Input Pin
In/Output Pin
Output: Open drain
11-12. IC601 IX1521GE
SOURCE DECODER
Pin No.
Pin name
Type
Direction
Function
22
HA[3:0]
I
I
Address bus input for microcomputer connection.
24-26
Used for register access and so on
HTYPE = L
It works as HR/W#(read/write) input terminal for connection to Motorola
HTYPE = L
It works as HR/W#(read/write) input terminal for connection to Motorola
27
HWR#
I
I
type microcomputer.
(HR/W#)
HTYPE = H
It works as HWR# (write) input terminal for connection to general purpose
microcomputer.
It works as HWR# (write) input terminal for connection to general purpose
microcomputer.
29
HCS#
I
I
Chip select input for connection to microcomputer
HTYPE = L
It works as HDS#(data strobe) input terminal for connection to Motorola
HTYPE = L
It works as HDS#(data strobe) input terminal for connection to Motorola
30
HRD#
I
I
type microcomputer.
(HDS#)
HTYPE = H
It works as HRD# (read) input terminal for connection to general purpose
microcomputer.
Bit stream input ready output terminal If the bit stream is input from
microcomputer, the terminal is bored.
For 3-state output, connect the pull-up resistor.
HRDY = L
It works as HRD# (read) input terminal for connection to general purpose
microcomputer.
Bit stream input ready output terminal If the bit stream is input from
microcomputer, the terminal is bored.
For 3-state output, connect the pull-up resistor.
HRDY = L
31
HRDY
3-S
O
Bit stream can not be input.
HRDY = H
The number of bytes which are set by CodBurstLen parameter can be
transferred from the microcomputer. During the time from transfer start of
the number of set bytes to transfer end, the terminal varies in 3 states.
HRDY = H
The number of bytes which are set by CodBurstLen parameter can be
transferred from the microcomputer. During the time from transfer start of
the number of set bytes to transfer end, the terminal varies in 3 states.
Microcomputer interface
11-12
DV-660S
DV-660H
DV-660H
Pin No.
Pin name
Type
Direction
Function
HTYPE = L
It works as HACK# (acknowledge) output terminal for connection to
It works as HACK# (acknowledge) output terminal for connection to
32
HACK#
Motorola type microcomputer.
(HR/W#)
It can be used as the weight terminal for connection to the general pur
pose microcomputer. For 3-state output, connect the pull-up resistor.
Interrupt request. If interrupt status register is read, interrupt is masked or
pose microcomputer. For 3-state output, connect the pull-up resistor.
Interrupt request. If interrupt status register is read, interrupt is masked or
34
HIRQ#
3-S
O
device is reset, the signal is deasserted.
For 3-state output, connect the pull-up resistor.
The bus width of the microcomputer interface If the device is worked as
CD-G decoder or CD-DSP is connected, select the 8-bit bus mode.
For 3-state output, connect the pull-up resistor.
The bus width of the microcomputer interface If the device is worked as
CD-G decoder or CD-DSP is connected, select the 8-bit bus mode.
35
HWID
I
I
Fix it before power up.
L=8bit bus mode
H=16bit bus mode
When HWID is H (16-bit bus MODE), byte order is set.
Setting is valid only when HWID is H.
L=8bit bus mode
H=16bit bus mode
When HWID is H (16-bit bus MODE), byte order is set.
Setting is valid only when HWID is H.
36
HORD
I
I
Fix it before power up.
L=HD [15:8] is regarded as m.s. byte. (Motorola type)
H=HD [7:0] is regarded as m.s. byte. (Intel type)
Bus type of microcomputer interface is set.
L=HD [15:8] is regarded as m.s. byte. (Motorola type)
H=HD [7:0] is regarded as m.s. byte. (Intel type)
Bus type of microcomputer interface is set.
37
HTYPE
I
I
Fix it before power up.
L=Motorola type
H=General purpose type
L=Motorola type
H=General purpose type
141
RESET#
I
I
RESET is input.
142
IDLE
3-S
O
It is output to indicate the idle state.
Microcomputer interface terminal list
Microcomputer interface
Pin No.
Pin name
Type
Direction
Function
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 15th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input bit clock from DC-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 14th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input the stream/PCM data from CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 13th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input frame synchronous signal from CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 12th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input error signal to CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 11th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to output the subcode reading clock to the
subcode interface of CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 10th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input subcode data from subcode interface of CD-DSP.
It works as the microcomputer data bus of 15th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input bit clock from DC-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 14th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input the stream/PCM data from CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 13th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input frame synchronous signal from CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 12th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input error signal to CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 11th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to output the subcode reading clock to the
subcode interface of CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 10th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input subcode data from subcode interface of CD-DSP.
Microcomputer / CD·subcode interface terminal list
Microcomputer interface / CD·subcode interface
3
HD15
3-S
I/O
(CDCLK)
(I)
(I)
4
HD14
3-S
I/O
(CDDAT)
(I)
(I)
5
HD13
3-S
I/O
(CDFRM)
(I)
(I)
6
HD12
3-S
I/O
(CDERR)
(I)
(I)
7
HD11
3-S
I/O
(SCCLK)
(O)
(O)
9
HD10
3-S
I/O
(SCDAT)
(I)
(I)
Function
General purpose terminal.
General input/output terminal. After resetting, it becomes the input direction.
General output terminal.
General input/output terminal. After resetting, it becomes the input direction.
General output terminal.
General port terminal list
Pin No.
Pin name
Type
Direction
2
GPSI
I
I
122-123
GPAIO[1:0]
3-S
I/O
159
GPSO
O
O
General port
11-13
DV-660S
DV-660H
DV-660H
Microcomputer / CD·subcode interface terminal list
Pin No.
Pin name
Type
Direction
Function
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 9th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input the subcode synchronous signal from the
subcode interface of CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 9th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input the frame synchronous signal from the
subcode interface of CD-DSP.
It works as the microcomputer data bus of 9th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input the subcode synchronous signal from the
subcode interface of CD-DSP.
When 16-bit bus width is selected, (HWID=low)
It works as the microcomputer data bus of 9th bit.
When 8-bit bus width is selected, (HWID=high)
It works as the terminal to input the frame synchronous signal from the
subcode interface of CD-DSP.
It works as the microcomputer bus of bits 7 thru 0.
10
HD9
3-S
I/O
(SCSYN)
(I)
(I)
11
HD8
3-S
I/O
(SCFRM)
(I)
(I)
12
14-17
HD[7:0]
3-S
I/O
19-21
Microcomputer interface / CD·subcode interface
PLL interface terminal list
Pin No.
Pin name
Type
Direction
126
GCLK1
I
I
128
XO
O
O
129
GCLK
I
I
135, 137 PLLCFG[1:0]
I
I
136
PLLCA
–
–
Pin No.
Pin name
Type
Direction
Function
Test terminal. Don’t connect it.
If quartz oscillator is connected to GCLK terminal, connect the other
terminal of quartz oscillator to this pin.
Master clock input terminal of device Input 27 MHz.
PLL is set. Before power-up, fix it.
External capacitor terminal for PLL.
If quartz oscillator is connected to GCLK terminal, connect the other
terminal of quartz oscillator to this pin.
Master clock input terminal of device Input 27 MHz.
PLL is set. Before power-up, fix it.
External capacitor terminal for PLL.
PLL interface
Pin No.
Pin name
Type
Direction
102
C7
3-S
O
(N.C.)
(3-S)
(O)
104
C6
3-S
O
(N.C.)
(3-S)
(O)
105
C5
3-S
O
(N.C.)
(3-S)
(O)
106
C4
3-S
O
(OSDPLT)
(3-S)
(I)
107
C3
3-S
O
(OSDPEL3)
(3-S)
(I)
Video/OSD interface terminal list
Pin No.
Pin name
Type
Direction
Function
Video8 register = 0
Color difference signal output terminal of 7th bit.
Video8 register = 1
The terminal becomes invalid.
Video8 register = 0
Color difference signal output terminal of 6th bit.
Video8 register = 1
The terminal becomes invalid.
Video8 register = 0
Color difference signal output terminal of 5th bit.
Video8 register = 1
The terminal becomes invalid.
Video8 register = 0
Color difference signal output terminal of 4th bit.
Video8 register = 1
Input terminal to select pallet table of OSD.
For OSDPLT=low, pallet table 0 is used.
For OSDPLT=high, pallet table 1 is used.
Video8 register = 0
Color difference signal output terminal of 3th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 3rd bit.
Color difference signal output terminal of 7th bit.
Video8 register = 1
The terminal becomes invalid.
Video8 register = 0
Color difference signal output terminal of 6th bit.
Video8 register = 1
The terminal becomes invalid.
Video8 register = 0
Color difference signal output terminal of 5th bit.
Video8 register = 1
The terminal becomes invalid.
Video8 register = 0
Color difference signal output terminal of 4th bit.
Video8 register = 1
Input terminal to select pallet table of OSD.
For OSDPLT=low, pallet table 0 is used.
For OSDPLT=high, pallet table 1 is used.
Video8 register = 0
Color difference signal output terminal of 3th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 3rd bit.
Video interface · OSD interface
11-14
DV-660S
DV-660H
DV-660H
Pin No.
Pin name
Type
Direction
Function
Video8 register = 0
Color difference signal output terminal of 2th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 2rd bit.
Video8 register = 0
Color difference signal output terminal of 1th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 1rd bit.
Video8 register = 0
Color difference signal output terminal of 0th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 0rd bit.
Color difference signal output terminal of 2th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 2rd bit.
Video8 register = 0
Color difference signal output terminal of 1th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 1rd bit.
Video8 register = 0
Color difference signal output terminal of 0th bit.
Video8 register = 1
It works as the OSD pallet data input terminal of 0rd bit.
109
C2
3-S
O
(OSDPEL2)
(3-S)
(I)
110
C1
3-S
O
(OSDPEL1)
(3-S)
(I)
111
C0
3-S
O
(OSDPEL0)
(3-S)
(I)
Video/OSD interface terminal list
Video interface · OSD interface
Pin No.
Pin name
Type
Direction
Function
Clock gained by dividing VCLK x 2 signal into halves.
Input terminal to switch video master/slave.
VMASTER=L
Video master mode. Video synchronizing signal and video clock are
internally generated.
HTYPE=H
Video slave mode. Video synchronizing signal and video clock are re
ceived from the external.
Video output enable input terminal
VDEN#=H
Y [7:0] and C [7:0] terminals are made to be disable (3-state).
VDEN#=L
Y [7:0] and C [7:0] terminals are made to be enable.
Note: C [7:0] terminal is the multiplexed terminal as OSDPLT [3:0] and so on.
For Video8 register = 0, VDEN# terminal is valid for Y [7:0] alone.
Composite blank output terminal. Horizontal/vertical blanking area and
polarity are programmable.
Input/output terminal of vertically synchronous signal. Polarity and synchronous
signal length are programmable.
Input/output terminal of horizontally synchronous signal.Polarity and
synchronous signal length are programmable.
Input/output terminal for identification of even/odd number field. Polarity is
programmable.
Video8 register = 0
Brightness signal output/input terminal.
Video8 register = 1
Brightness/color difference multiplex terminal as ITU-T656
Terminal to input video clock or output 27 MHz.
Input terminal to switch video master/slave.
VMASTER=L
Video master mode. Video synchronizing signal and video clock are
internally generated.
HTYPE=H
Video slave mode. Video synchronizing signal and video clock are re
ceived from the external.
Video output enable input terminal
VDEN#=H
Y [7:0] and C [7:0] terminals are made to be disable (3-state).
VDEN#=L
Y [7:0] and C [7:0] terminals are made to be enable.
Note: C [7:0] terminal is the multiplexed terminal as OSDPLT [3:0] and so on.
For Video8 register = 0, VDEN# terminal is valid for Y [7:0] alone.
Composite blank output terminal. Horizontal/vertical blanking area and
polarity are programmable.
Input/output terminal of vertically synchronous signal. Polarity and synchronous
signal length are programmable.
Input/output terminal of horizontally synchronous signal.Polarity and
synchronous signal length are programmable.
Input/output terminal for identification of even/odd number field. Polarity is
programmable.
Video8 register = 0
Brightness signal output/input terminal.
Video8 register = 1
Brightness/color difference multiplex terminal as ITU-T656
Terminal to input video clock or output 27 MHz.
84
VCLK
3-S
I/O
85
VMASTER
I
I
87
VDEN#
I
I
88
CBLANK
O
O
89
VSYNC
3-S
I/O
90
HSYNC
3-S
I/O
91
FI
3-S
I/O
92
94-97
Y[7:0]
3-S
O
99-101
124
VCLK X 2
3-S
I/O
Video interface terminal list
Video interface
Pin No.
Pin name
Type
Direction
Function
Audio (PCM) input terminal.
Stereo x1
Audio (PCM) output terminal.
Stereo x3
S/PDIF output terminal AC-3 stream or PCM stream can be output.
Moreover, it works as the audio output terminal of 7th and 8th channels
Left/Right clock output terminal of AOUT [2:0] and AIN.
The polarity is programmable.
Bit clock output terminal of AOUT [2:0] and AIN.
The polarity is programmable.
Audio master clock input/output terminal.
256 Fs or 386 Fs can be used.
Stereo x1
Audio (PCM) output terminal.
Stereo x3
S/PDIF output terminal AC-3 stream or PCM stream can be output.
Moreover, it works as the audio output terminal of 7th and 8th channels
Left/Right clock output terminal of AOUT [2:0] and AIN.
The polarity is programmable.
Bit clock output terminal of AOUT [2:0] and AIN.
The polarity is programmable.
Audio master clock input/output terminal.
256 Fs or 386 Fs can be used.
Audio interface terminal list
Pin No.
Pin name
Type
Direction
112
AIN
I
I
114-116
AOUT[2:0]
O
O
117
S/PDIF
O
O
(AOUT[3])
118
ALRCLK
O
O
119
ABCLK
O
O
132
AMCLK
3-S
I/O
Audio interface
11-15
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