Sharp HT-CN500DVH (serv.man7) Service Manual ▷ View online
– 45 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
1
GND-SUB
Substrate ground.
2, 3
OUT2B
Output half bridge 2B.
4
VCC2B
Positive supply.
5
GND2B
Negative supply.
6
GND2A
Negative supply.
7
VCC2A
Positive supply.
8, 9
OUT2A
Output half bridge 2A.
10, 11
OUT1B
Output half bridge 1B.
12
VCC1B
Positive supply.
13
GND1B
Negative supply.
14
GND1A
Negative supply.
15
VCC1A
Positive supply.
16, 17
OUT1A
Output half bridge 1A.
18*
N.C.
Not connected.
19
GND-clean
Logical ground.
20
GND-Reg
Ground to regulator VDD.
21, 22
VDD
5 V regulator reference to ground.
23
IBIAS
High logical state setting voltage.
24
CONFIG
Configuration pin.
25
PWRDN
Stand-by pin.
26
TRI-STATE
Hi-Z pin.
27
FAULT
Fault pin advisor.
28
TH-WAR
Thermal warning advisor.
29
IN1A
Input of half bridge 1A.
30
IN1B
Input of half bridge 1B.
31
IN2A
Input of half bridge 2A.
32
IN2B
Input of half bridge 2B.
33, 34
VSS
5 V regulator reference to + VCC.
35, 36
VCC Sign
Signal positive supply.
Port Name
Pin No.
Function
IC500, IC501, IC502 92LRCI0505-001: Power Amp. (STA505)
– 46 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
1
CAP
Customer OP amplifier + input.
2
VCC
Power pin (for DPD).
3
PDRF
Pickup signal input.
4-7
PD1-PD4
Pickup signal input.
8
GND
Ground (for DPD).
9, 10
FIN1, FIN2
Pickup signal input.
11*, 12*
PIN1, PIN2
Pickup signal input.
13, 14
TIN1, TIN2
Pickup signal input.
15
LDD1
AP1 input.
16
LDS1
APC1 monitor input.
17
LDD2
APC2 output.
18
LDS2
PC2 monitor input.
19
GND
Ground (servo system).
20
LDTH
APC1 threshold changeover (H: VCC-1.5 V, L: 180 mV).
21
LDON1
APC1 laser ON pin (H: ON).
22
LDON2
APC2 laser ON pin (H: ON).
23
AGOF
RFAGC OFF pin (H: OFF).
24
BCA
PH discharge factor changeover (H: BCA mode).
25
GU
RF, servo signal gain-up pin (H: gain-up).
26
DVD/CD
RF-equalizer band changeover pin (H: DVD).
27
DPD/TE
TE output changeover pin (H: DPD).
28
WO/PP
WO output changeover pin (H: wobble).
29
VCC
Power pin (servo system).
30
TH
Tracking hold (H: hold).
31
XHTR
Tracking, bottom band changeover (L: high band).
32
SGC
Servo gain control pin (RREC, FE, PP, TE).
33
BST
Equalizer boost control pin.
34
FC
Equalizer fo control pin.
35
FEBL
FE balance control pin.
36
TEBL
TE balance control pin.
37
CP
Pin to connect resistor and capacitor to set charge pump gain.
38
RREC
Reflection output.
39
FE
Focus error output.
40
TE
Tracking error output.
41
WO
Wobble/push-pull output pin.
42
PP
Push-pull output pin.
43
PPN
Pin to connect resistor to set push-pull gain.
44
WOC
DC cut capacity connection pin.
45
ISET
Pin to connect resistor to set BPF central frequency.
46
BH RF
bottom detection output.
47
PH
RF peak detection output.
48
SREFI
SREF setting pin.
49
BCAI
Pin to connect resistor to set the peak hold detection constant.
50
PHC
Pin to connect PH detection capacitor for RF-AGC.
51
SREF
Reference voltage output for servo signal.
52
LPC
Pin to connect capacitor for RF DC servo.
53*
N/C
N/C pin.
54
RFON
RF - output.
55
RFOP
RF + output.
56
GND
Ground.
57
FSET
Pin to connect resistor to set equalizer fo frequency.
58
RREF
Reference voltage output (for pick).
Port Name
Pin No.
Function
IC802 92LRCI09703-001: DVD Players RF Amp. (LA9703W) (2/1)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 47 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
Port Name
Pin No.
Function
IC802 92LRCI09703-001: DVD Players RF Amp. (LA9703W) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
59
RFN
RF signal - input.
60*
N/C
N/C pin.
61
RFP
RF + signal.
62
CAO
Customer OP amplifier output pin.
63
VCC
Power pin (RF system).
64
CAN
Customer OP amplifier - input pin.
FM
S-METER
AM
S-METER
S-CURVE
SD
COMP
AM IF
AGC
ALC
BUFF
AM
OSC
REG
AM
MIX
AM
RF.AMP
DET
AM/FM
IF-BUFF
AM IF
FM
DET
TUNING
DRIVE
STEREO
DRIVE
3 rd 5 th
DECODER
ANTI-BIRDIE
P-DET
Ø
STEREO
SW
VCO
304kHz
FF
38 k
PILOT
DET
MUTE
FF
19k
GND
VCC
FF
19k
2
π
θ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Figure 47 BLOCK DIAGRAM OF IC
IC001 92LRCI1837-001: (LA1837)
– 48 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC106 92LRCI6028-001: Microcomputer (ES6028) (1/5)
1
VEE
Input
I/O power supply.
2-7
LA4-LA9
Output
Device address output.
8
VSS
Input
Ground.
9
VCC
Input
Core power supply.
10-16
LA10-LA16
Output
Device address output.
17
VSS
Input
Ground.
18
VEE
Input
I/O power supply.
19-22*,23* LA17-LA21
Output
Device address output.
24
RESET#
Input
Reset input, active low.
25
TDMDX
Output
TDM transmit data.
RSEL
Input
ROM Select.
26
VSS
Input
Ground.
27
VEE
Input
I/O power supply.
28
TDMDR
Input
TDM receive data.
29
TDMCLK
Input
TDM clock input.
30
TDMFS
Input
TDM frame sync.
31*
TDMTSC#
Output
TDM output enable.
32
TWS
Output
Audio transmit frame sync.
SEL_PLL2
Input
System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
33
TSD0
Output
Audio transmit serial data port 0.
SEL_PLL0
Input
Refer to the description and matrix for SEL_PLL2 pin 32.
34
VSS
Input
Ground.
35
VCC
Input
Core power supply.
36
TSD1
Output
Audio transmit serial data port 1.
SEL_PLL1
Input
Refer to the description and matrix for SEL_PLL2 pin 32.
37
TSD2
Output
Audio transmit serial data output 2.
38*
TSD3
Output
Audio transmit serial data output 3
39
MCLK
Input/Output
Audio master clock for audio DAC.
40
TBCK
Output
Audio transmit bit clock.
41
SPDIF
Output
S/PDIF output.
SEL_PLL3
Input
Clock source select.
42*
N.C.
No connect pins. Leave open.
43
VSS
Input
Ground.
44
VCC
Input
Core power supply.
45*
RSD
Input
Audio receive serial data.
46*
RWS
Input
Audio receive frame sync.
47*
RBCK
Input
Audio receive bit clock.
48*
N.C.
No connect pins. Leave open.
49
XIN
Input
Crystal input.
50
XOUT
Output
Crystal output.
51
AVEE
Input
Analog power for PLL.
52
VSS
Input
Ground.
53
DMA0
Output
DRAM address bus 0.
54
DMA1
Output
DRAM address bus 1.
55
DMA2
Output
DRAM address bus 2.
56
DMA3
Output
DRAM address bus 3.
57
DMA4
Output
DRAM address bus 4.
58
DMA5
Output
DRAM address bus 5.
59
VEE
Input
I/O power supply.
60
VSS
Input
Ground.
61
DMA6
Output
DRAM address bus 6.
62
DMA7
Output
DRAM address bus 7.
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
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