Sharp HT-CN500DVH (serv.man7) Service Manual ▷ View online
– 41 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC003 92LRCI7272-002: (LC72720NM)
1
VREF
Output
Reference voltage output (VDDA/2).
2
MPXIN
Input
Baseband (multiplexed ) signal input.
3
VDDA
—
Analog system power supply (+5 V).
4
VSSA
—
Analog system ground.
5
FLOUT
Output
Subcarrier output (filter output).
6
CIN
Input
Subcarrier input (comparator input).
7
T1
Input
Test input (This pin must always be connected to ground.).
8
T2
Input
Test input (stand-by control).
0: Normal operation, 1: Stand-by state. (crystal oscillator stopped).
0: Normal operation, 1: Stand-by state. (crystal oscillator stopped).
9*
T3 (RDCL)
Input/Output* Test I/O (RDS clock output).
10*
T4 (RDDA)
Input/Output* Test I/O (RDS data output).
11*
T5 (RSFT)
Input/Output* Test I/O (Soft-decision control data output).
12
XOUT
Output
Crystal oscillator output (4.332/8.664 MHz).
13
XIN
Input
Crystal oscillator input. (external reference signal input).
14
VDDD
—
Digital system power supply (+5 V).
15
VSSD
—
Digital system ground.
16*
T6
Input/Output* Test I/O (Error status output, regenerated carrier output, error block count output).
(ERROR/57K/BE1)
17*
T7
Input/Output* Test I/O(Error correction status output, SK detection output, error block count output).
(CORREC/
ARI-ID/BE0)
ARI-ID/BE0)
18*
SYNC
Input/Output* Block synchronization detection output.
19*
RDS-ID
Output
RDS detection output.
20
DO
Output
Data output. Serial data interface (CCB).
21
CL
Input
Clock output. Serial data interface (CCB).
22
DI
Input
Data input. Serial data interface (CCB).
23
CE
Input
Chip enable. Serial data interface (CCB).
24
SYR
Input
Synchronization and RAM address reset (active high).
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.
VDDA
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
CCB
TEST
VREF
FLOUT
CIN
57 kHz
BPF
(SCF)
SMOOTHING
FILTER
RAM
(24 BLOCK DATA)
ERROR CORRECTION
(SOFT DECISION)
CLK(4.332 MHz)
XIN
XOUT
OSC/DIVIDER
VREF
PLL
(57 kHz)
CLOCK
RECOVERY
(1187.5 Hz)
VDDD
VSSD
RDS-ID
SYNC
SYR
DATA
DECODER
SYNC/CE CONTROLLER
SYNC
DETECT-1
SYNC
DETECT-2
MEMORY
CONTROL
VSSA
MPXIN
DO
CL
DI
CE
T1
T2
T3~T7
+
–
Figure 41 BLOCK DIAGRAM OF IC
– 42 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC110 92LRCI8772-001: 6CH D/A 2CH A/D (WM8772)
1
MODE
Digital input
Control format selection.
0= Software control.
1= Hardware control.
0= Software control.
1= Hardware control.
2
MCK
Digital input
Master clock; 256, 384, 512 or 768 fs (fs= word clock frequency).
3
BCLK
Digital input/output
Audio interface bit clock.
4
LRC
Digital input/output
Audio left/right word clock.
5
DVDD
Supply
Digital positive supply.
6
DGND
Supply
Digital negative supply.
7
DIN1
Digital input
DAC channel 1 data input.
8
DIN2
Digital input
DAC channel 2 data input.
9
DIN3
Digital input
DAC channel 3 data input.
10
DOUT
Digital output
ADC data output.
11
ML/I2S
Digital input
Software Mode: Serial interface Latch signal.
Hardware Mode: Input Audio Data Format.
Hardware Mode: Input Audio Data Format.
12
MC/IWL
Digital input
Software Mode: Serial control interface clock.
Hardware Mode: Audio data input word length.
Hardware Mode: Audio data input word length.
13
MD/DM
Digital input
Software Mode: Serial interface data.
Hardware Mode: De-emphasis selection.
Hardware Mode: De-emphasis selection.
14*
MUTE
Digital input/output
DAC Zero Flag output or DAC mute input.
15
REFADC
Analogue output
ADC reference buffer decoupling pin; 10
µ
F external decoupling.
16
VREFN
Supply
ADC and DAC negative supply and substrate connection.
17
VREFP
Supply
DAC positive reference supply.
18
VMID
Analogue output
Midrail divider decoupling pin; 10
µ
F external decoupling.
19
AINR
Analogue input
ADC right input.
20
AINL
Analogue input
ADC left input.
21
VOUT1L
Analogue output
DAC channel 1 left output.
22
VOUT1R
Analogue output
DAC channel 1 right output.
23
VOUT2L
Analogue output
DAC channel 2 left output.
24
VOUT2R
Analogue output
DAC channel 2 right output.
25
VOUT3L
Analogue output
DAC channel 3 left output.
26
VOUT3R
Analogue output
DAC channel 3 right output.
27
AGND
Supply
Analogue negative supply and substrate connection.
28
AVDD
Supply
Analogue positive supply.
Port Name
Pin No.
Input/Output
Function
Note: Digital input pins have Schmitt trigger input buffers.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DACVREFN
VMID
DVDD
DGND
MUTE
MODE
ML/I2S
MC/IWL
MD/DM
DACVREFP
REFADC
ADCVREFN
ADCMCLK
DOUT
ADCLRC
DACLRC
ADCBCLK
AACBCLK
DIN1
DIN2
DIN3
DACMCLK
AVDD
AGND
VOUT1L
VOUT1R
VOUT2L
VOUT2R
VOUT3L
VOUT3R
STEREO
ADC
STEREO
DAC
LOW
PASS
FILTER
LOW
PASS
FILTER
LOW
PASS
FILTER
STEREO
DAC
STEREO
DAC
VREFN
VREFP
AUDIO
INTERFACE
&
DIGITAL
FILTERS
CONTROL INTERFACE
AINL
AINR
+
–
Figure 42 BLOCK DIAGRAM OF IC
– 43 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC503 92LRCI0308-001: Audio Processor (STA308) (1/2)
1
MVO
Input
Master Volume Override.
2
GND
—
Digital Ground.
3
VDD3
—
3.3 V Digital Supply.
4
GND
—
Digital Ground.
5
VDD
—
2.5 Digital Supply.
6
SDI_78
Input
Input I2S Serial Data Channels 7 & 8.
7
SDI_56
Input
Input I2S Serial Data Channels 5 & 6.
8
SDI_34
Input
Input I2S Serial Data Channels 3 & 4.
9
SDI_12
Input
Input I2S Serial Data Channels 1 & 2.
10
LRCKI
Input
Input I2S Left/Right Clock.
11
BICKI
Input
Input I2S Serial Clock.
12
VDD3
—
3.3 V Digital Supply.
13
GND
—
Digital Ground.
14
VDD
—
2.5 Digital Supply.
15
RESET
Input
Global Reset.
16
PLLB
Input
PLL Bypass.
17
SA
Input
Select Address (I2C).
18
SDA
Input/Output
I2C Serial Data.
19
SCL
Input
I2C Serial Clock.
20
XTI
Input
Crystal Oscillator Input (Clock Input).
21
FILTER_PLL
PLL Filter.
22
VDDA
PLL 2.5 V Supply.
23
GNDA
PLL Ground.
24
VDD3
—
3.3 V Digital Supply.
25*
CKOUT
Output
Clock Output.
26
VDD
—
2.5 Digital Supply.
27
GND
—
Digital Ground.
28
VDD3
—
3.3 V Digital Supply.
29*
OUT8_B
Output
PWM Channel 8 Output B.
30*
OUT8_A
Output
PWM Channel 8 Output A.
31*
OUT7_B
Output
PWM Channel 7 Output B.
32*
OUT7_A
Output
PWM Channel 7 Output A.
33
OUT6_B
Output
PWM Channel 6 Output B.
34
OUT6_A
Output
PWM Channel 6 Output A.
35
VDD3
—
3.3 V Digital Supply.
36
GND
—
Digital Ground.
37
VDD
—
2.5 Digital Supply.
38
OUT5_B
Output
PWM Channel 5 Output B.
39
OUT5_A
Output
PWM Channel 5 Output A.
40
OUT4_B
Output
PWM Channel 4 Output B.
41
OUT4_A
Output
PWM Channel 4 Output A.
42
OUT3_B
Output
PWM Channel 3 Output B.
43
OUT3_A
Output
PWM Channel 3 Output A.
44
VDD3
—
3.3 V Digital Supply.
45
GND
—
Digital Ground.
46
VDD
—
2.5 Digital Supply.
47
OUT2_B
Output
PWM Channel 2 Output B.
48
OUT2_A
Output
PWM Channel 2 Output A.
49
OUT1_B
Output
PWM Channel 1 Output B.
50
OUT1_A
Output
PWM Channel 1 Output A.
51
EAPD
Output
External Amplifier Power Down.
52
VDD3
—
3.3 V Digital Supply.
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 44 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
53
GND
—
Digital Ground.
54
VDD
—
2.5 Digital Supply.
55*
BICKO
Output
Output l2S Serial Clock.
56*
LRCKO
Output
Output l2S Left/Right Clock.
57*
SDO_12
Output
Output l2S Serial Data Channel 1 & 2.
58*
SDO_34
Output
Output l2S Serial Data Channel 3 & 4.
59
VDD3
—
3.3 V Digital Supply.
60
GND
—
Digital Ground.
61
VDD
—
2.5 Digital Supply.
62*
SDO_56
Output
Output l2S Serial Data Channel 5 & 6.
63*
SDO_78
Output
Output l2S Serial Data Channel 7 & 8.
64
PWDN
Input
Device Powerdown.
IC503 92LRCI0308-001: Audio Processor (STA308) (2/2)
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
LRCK1
BICK1
SDI12
SDI34
SDI56
SDI78
PLLB
XTI
CKOUT
PWND
EAPD
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT7A/B
OUT8A/B
LRCKO
LICKO
SDO12
LICKO
SDO12
SDO34
SDO56
SDO78
SA
SERIAL
DATA
IN
CHANNEL
MAPPING
SYSTEM TIMING
PLL
POWER
DOWN
VARIABLE
DOWN-
SAMPLING
VARIABLE
OVER.
SAMPLING
TREBL,
BASS, EQ
(BIQUADS)
VOLUME
LIMITING
DDX
SERIAL
DATA
OUT
SYSTEM
CONTROL
OVERSAMPLING
I C
SCL
SDA
MVO
2
Figure 44 BLOCK DIAGRAM OF IC
IC107 92LRCI2402-002: EEP ROM (TA24C02N)
1
N.C.
No Connection.
2, 3
A0, A1
Address inputs.
4
N.C.
No Connection.
5
A2
Address inputs.
6
GND
7, 8
N.C.
No Connection.
9
SDA
Serial data.
10
SCL
Serial clock input.
11
N.C.
No Connection.
12
WP
Write protect.
13
VCC
14
N.C.
No Connection.
Port Name
Pin No.
Function
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