Panasonic KX-TPA65RU / KX-TPA65RUB Service Manual ▷ View online
9
KX-TPA65RU/KX-TPA65RUB
Start up of IC1
1.8V_1 rises up after output of IC7 for reset of IC1is Hi-level when VCC of IC1 is about 3.2V.
Then system clock circuit starts, which buffer output is a signal at test point "BCLK".
At last ,1.2V_1 rises up.
After power for IC1 is stable, IC1 starts to boot.
Then system clock circuit starts, which buffer output is a signal at test point "BCLK".
At last ,1.2V_1 rises up.
After power for IC1 is stable, IC1 starts to boot.
Start up of IC2
IC2 starts up by self power on reset circuit when VCC of IC2 is about 3.2V.
But IC2 restarts after IC2 receives reset signal from IC1.
This is when BCLK is stable and 1.2V_2 rises up after 1.8V_2.
But IC2 restarts after IC2 receives reset signal from IC1.
This is when BCLK is stable and 1.2V_2 rises up after 1.8V_2.
About 1.8s later, IC1 raises level of BOOT signal to IC2.
And setting data for IC2 is send to IC2 in SPIM bus as follow steps.
IC1 outputs TXREQ2 Hi-level to IC2.
IC2 replies READY1 Hi-level to IC1.
IC1 outputs SPIM_/CS Low-level.
IC1 outputs SPIM_CLK and sends data on SPIM_DO coincident with SPIM_CLK.
And setting data for IC2 is send to IC2 in SPIM bus as follow steps.
IC1 outputs TXREQ2 Hi-level to IC2.
IC2 replies READY1 Hi-level to IC1.
IC1 outputs SPIM_/CS Low-level.
IC1 outputs SPIM_CLK and sends data on SPIM_DO coincident with SPIM_CLK.
VCC of IC1
1.2V_1
1.8V_1
BCLK
VCC of IC2
IC2 RSTN
1.2V_2
1.8V_2
IC2 RSTN
TXREQ2
READY1
BOOT
1.8s
TXREQ2
READY1
SPIM_/CS
SPIM_CLK
SPIM_/CS
SPIM_CLK
SPIM_DO
SPIM_DI
0.31us
10
KX-TPA65RU/KX-TPA65RUB
4.3.4.
Clock Circuit
Main system clock (13.824MHz) is generated from X1, and Oscillation circuit consists of X1 and IC1.
The clock is buffered out to IC2 by IC6.
IC1 and IC2 have PLL circuits inside and generate clocks for operations.
The clock is buffered out to IC2 by IC6.
IC1 and IC2 have PLL circuits inside and generate clocks for operations.
4.3.5.
Bus Access
The program for IC1, adjustment data,and temporary user data has been stored in IC4.
The program for IC2 has been stored in IC5.
1.8V for IC4 is supplied by IC1 and 1.8V for IC5 is supplied by IC2.
The program for IC2 has been stored in IC5.
1.8V for IC4 is supplied by IC1 and 1.8V for IC5 is supplied by IC2.
X1
13.824MHz
13.824MHz
IC1
Main MPU
Main MPU
IC6
CLK Buffer
CLK Buffer
IC2
Sub MPU
Sub MPU
IC4
QSPl Flash
QSPl Flash
103.68MHz
IC5
QSPI Flash
QSPI Flash
103.68MHz
LCD circuit
8.64MHz
TDM SCLK
2.3MHz
KEY circuit
34.6kHz
SPIM_CLK
3.2MHz
IC4, 5
FLASH
(64Mbit)
DQ[3:0]
*CS
CL
QSPI_CLK
QSPI_IO[3:0]
QSPI_/CS
IC1, 2
DCX81
DQ[3:0]
QCSN0
QSCLK
(QSPI Data)
11
KX-TPA65RU/KX-TPA65RUB
4.3.6.
LCD Circuit
The LCD is controlled by SPI (LCD_SCL, LCD_/RST, LCD_/CS, LCD_SID, LCD_CD).
LCD back-light has 3 modes which currents are controlled by IC1.
LCD back-light has 3 modes which currents are controlled by IC1.
4.3.7.
LED Circuit
IC1 controls Ringer LED on sub P.C.B.
LCD_SCL
LCD_SID
LCD_CD
LCD_BL2
LCD_BL1
C133
CN1
8
NCS
CN1
1
LED2
CN1
11
VCI
C134
CN1
10
DNC_SCL
CN1
7
DB0_SDA
CN1
4
VSSA
CN1
3
4V
CN1
9
NRESET
CN1
5
IOVCC
D3.2V
CN1
2
LED1
CN1
6
NWR_RNW
R118
DG
4.5V
C135
DG
C136
C140
C431
C432
128x160dot
To 1.8 TFT Color LCD
LCD_CS
LCD_RST
IC1
9
8
10
3
4
30
27
LCD_/CD
LCD_SCL
LCD_SID
LCD_/CS
5.8ms
0.88us
C132
DG
RINGER_LED_K
4.5V
LED1
R117
BELL BLUE
IC1
4
12
KX-TPA65RU/KX-TPA65RUB
4.3.8.
Key Scan
The key data is under the matrix control by IC1.
When key is pushed, corresponding pins of IC1are connected and those signals are same.
When IC1detects key pushed, it controls IC2 to output BEEP sound in SPIM BUS.
Then IC2 makes BEEP sound and outputs it to a Speaker.
When key is pushed, corresponding pins of IC1are connected and those signals are same.
When IC1detects key pushed, it controls IC2 to output BEEP sound in SPIM BUS.
Then IC2 makes BEEP sound and outputs it to a Speaker.
<KEY Matrix>
Note
Refer to 4.3.11 as to Speaker of Speaker phone.
PIN (IC1)
88
89
90
91
94
95
66
96
87
RIGHT
LEFT
UP
LINE
SOFTA
VOLUP
VOLDOWN
SP-PHONE
88
-
MSESSAGE
DOWN
*
7
4
1
MUTE
89
-
-
ENTEA
0
8
5
2
CONF
90
-
-
-
#
9
6
3
REDIAL
91
-
-
-
-
SOFTB
HOLD
FUNCTION
-
94
-
-
-
-
-
SOFTC
TANSFER
-
95
-
-
-
-
-
-
CANCEL
-
KBIO_5
KBIO_3
KBIO_6
KBIO_1
KBIO_7
KBIO_8
KBIO_9
KBIO_2
KBIO_4
UP
1
2
DOWN
1
2
MESSAGE
1
2
ENTER
1
2
LINE
1
2
*
1
2
0
1
2
#
1
2
9
1
2
SOFTB
1
2
8
1
2
7
1
2
SOFTA
1
2
6
1
2
SOFTC
1
2
2
1
2
5
1
2
CANCEL
1
2
TRANSFER
1
2
SP-PHONE
1
2
REDIAL
1
2
MUTE
1
2
CONF
1
2
1
1
2
3
1
2
FUNCTION
1
2
HOLD
1
2
4
1
2
RIGHT
1
2
LEFT
1
2
VOLUP
1
2
VOLDOWN
1
2
IC1
IC2
87
88
89
90
91
94
95
96
66
TXREQ_2
SPIM_DO
READY_1
75
98
81
80
100
73
SPIM_DI
99
76
SPIM_CS
101
77
SPIM_CLK
102
78
28
30
TP(SPP)
TP(SPM)
BEEP signal
example
example
C23
C24
D3.2V
C27
C28
DG1
DG3
DG4
SPM
SPP
URX1
URX2
UTX1
UTX2
C3
C4
C5
C7
C8
C9
HSSP+
HSSP-
D1
HSMIC+
HSMIC-
L303
L304
JK2
CN10
CN11
VIN1
VIN2
R315
L1
R316
IC3
R10
C319 C320
C322
C323
C326 C327
Q1
R3
R5
R7
R8
D301
D303D304
D305
D306
C10
C11
C12
C14
C12
C14
R214
R128
C340
5
1
4
1
3
1
3
VIA Holes connected to
pins of IC1 as for key scan
pins of IC1 as for key scan
94
89
91
66
88
90
96
87
95
66
95
66
95
20ms
0.47ms
(two signals are different)
(two signals are same.)
FREE STATE
KEY pushed
< Aleternation of Key scan signal in case of "CANCEL" key >
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