Panasonic KX-TCD965GC Service Manual ▷ View online
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KX-TCD965GC
BLOCK DIA
GRAM RF UNIT (B
ASE UNIT)
Fig. 17
Doubler
BPF
1.89GHz
TR Switch
Ant. Switch
RF
Amp
112.32MHz
BPF
BPF=Bandpass Filter
LPF=Low Pass Filter
LPF=Low Pass Filter
Mixer
Phase-Lock-Loop
Tx
Buffer
PA
Switch
P.A.
SAW
BPF
IF
Amp
RSSI
DC
Comp
IF
Amp
Det.
VCO
Buff.
DC Contr.
Rx/Tx
3V
Reg.
3V
Data
LPF
945MHz
1.89GHz
10.368MHz
4V-FILT
SLICE OUT
31
SLICE CTRL
30
RSSI
32
SYS CLOCK
34
PLL ENABLE
22
PLL DATA
21
PLL CLOCK
20
PLL PD
12
Vcc OC
18
RF ON
8
Rx DATA
29
Tx DATA
19
Vcc PA (4V)
5
,
4
PLL PWR DWN
17
Tx/Rx SWITCH
2
ANT SW2
40
ANT SW1
3
PA RAMP
39
RF1
49
RF2
42
RF2
42
GND
43
GND
44
GND
45
GND
46
GND
47
GND
48
RF1
49
GND
15
NC
14
NC
13
PLL PD
12
NC
11
GND
10
GND
9
RF ON
8
GND
7
GND
6
Vcc PA
5
Vcc PA
4
ANT SW1
3
Tx/Rx SWITCH
2
GND
1
GND
26
GND
27
GND
28
Rx DATA
29
SLICE CTRL
30
SLICE OUT
31
RSSI
32
GND
33
SYS CLOCK
34
GND
35
GND
36
GND
37
GND
38
PA RAMP
39
ANT SW2
40
GND
41
GND
25
GND
24
GND
23
PLL ENABLE
22
PLL DATA
21
PLL CLOCK
20
Tx DATA
19
Vcc OC
18
PLL PWR DWN
17
NC
16
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KX-TCD965GC
Fig. 18
BLOCK DIA
GRAM B
ASEB
AND SECTION AND LINE INTERF
A
C
E
(B
ASE UNIT)
ASE UNIT)
85
IC103
EEPROM
Micro-
controller
controller
IC102
Flash
Flash
PROM
27/26
66
DATA
14
6
5
7
32
SYS-CLK
Tx-DATA
Rx-DATA
PLL-CLK
RST
SERIAL
INPUT/OUTPUT
INPUT/OUTPUT
WR
OE
OE
30
CE
RESET
19
11
25
20
22
21
X101
D104
DAC
10.368MHz
Ear.
Amp
Amp
DAC
ADC
Clock
+Data
Recov
+Data
Recov
Gaus
Filter
RSSI
ADC
ADC
DTMF
Gen.
Gen.
15
92
83
Clock
Gen.
Gen.
BMC
IC101
BBIC
44
32
40
PAUSE-DIAL
46
EARTH
39
HOOK
34
RING
30
CHARGE-PULSE
IC105
FLASH ROM
SLICE-OUT
RSSI
24
23
23
PLL-DAT
PLL-ENABLE
PLL-ENABLE
7
PLL-PD
5
4
4
RFON
PA-AMP
PA-AMP
3
Tx/Rx-SW
2
ANT-SW1
8
ANT-SW2
63
62
58
RXAF
TXAF
HOOK
60
T13
J103
J102
Serial
Data
Data
Clock
Mic.
Amp
Amp
Line
Amp
Amp
Earth
Recall
RLY1
Recall
RLY1
Buf.
T2
T2
D8
A
B
A
4
3
1
5
2
6
J1
Tel.
Line
Line
Not
German
Version
German
Version
B
E
T8, T9
Hook
Switch
Hook
Switch
Line Profection
& 16 kHz Notch Filter
& 16 kHz Notch Filter
Bridge
Rect.
Rect.
IC2
T11,
T12
T12
IC4
IC3
EARTH
CHARGE
RING
-PULSE
-PULSE
PAUSE-DIAL
Bell
Det.
Det.
DC
Mask
Mask
C.P.
Det.
Det.
CLIP
CILP
ADDRESS
Charge
Contacts
Contacts
T16
VUNREG
+4V
+3V
RESET
IC7
T14, T15
3.3V
Reg.
Reg.
T16
Charge
Det.
Det.
4V
Reg.
Reg.
Charge
Circuit
Circuit
1
2
3
6
5
4
J2
AC
Adaptor
Adaptor
Charge
LED
LED
DATA
IC501
SUB CPU
LED
ANSWER LED
CALLER ID LED
IN USE LED
CALLER ID LED
IN USE LED
LCD
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KX-TCD965GC
2. THE BASE-BAND SECTION (SEE BLOCK DIAGRAM Fig. 18)
2.1 INTRODUCTION
The base-band section consists of a base-band integrated circuit (BBIC), a Flash PROM, an EEPROM, and an AND
Gate.
2.2 THE BASE-BAND INTEGRATED CIRCUIT (BBIC)
The PQVINSC14424 (IC101) is a CMOS device designed to handle all the audio, signal and data processing needed
in a DECT base unit. It contains a “burst mode controller” microprocessor which takes care of DECT specific physical
layer and radio section control. It also contains two ADPCM transcoders, a low power 14 bit codec (ADC/DAC), vari-
ous other ADC’s, DAC’s and timers, a gaussian filter for the DECT GFSK modulation method, clock and data recovery
circuits, a clock oscillator circuit, a DTMF generator (DSP), an echo suppression circuit (DSP), and a pair of gain
controllable audio amplifiers for line input and line output.
The IC101 interfaces to its external PROM (IC102) via a data/address/control bus. It connects to the EEPROM via a
serial interface, and a second serial interface is used during manufacture and service to connect to an external com-
puter.
2.3 FLASH PROM (SEE Fig. 19)
The 2 Mbit (IC102) Flash PROM contains the operational firmware for the microcontroller. It is interfaced to the
data/address/control bus using address lines A0 to A16, data lines D0 to D7, and chip select (pin 30), output enable
(pin 32), and write (pin 7).
2.4 EEPROM (SEE Fig. 19)
The electrically erasable PROM PQVINM4C32L (IC103) is used to store all the temporary operating parameters for
the base. It uses a two-line serial data interface with the BBIC, with bi-directional data on pin 5, and clock on pin 6.
2.5 CLOCK GENERATION (SEE Fig. 19)
A single clock generator in the BBIC uses an external crystal X101 to derive all clock frequencies used in the base.
The crystal is tuned to the exact frequency of 10.368 MHz during manufacture by feeding a DC voltage from a DAC in
the microcontroller (from pin 14 of IC101) to the varicap diode D104.
The BBIC provide buffered clock signals RFCLK (pin 11) at 10.368 MHZ for the Frequency Synthesizer, which is only
active during the PLL lock period. Other clock is SCLK on pin 1 (3.456MHz). The basic data rate for TRADAT and
RECDAT is 1.152 Mbits/s, which is 10.368 MHs divided by 9. The data rate for the serial interface to the phase-lock-
loop is also 1.152 Mbits/s.
CIRCUIT OPERATION (BASE UNIT)
1. R.F. SECTION (SEE BLOCK DIAGRAM Fig. 17)
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KX-TCD965GC
Fig. 19-1
Circuit Diagram
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