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49

1. P = Power supply.
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.

21

COL/RMII

Ipd/O

Mll Collision Detect Output. 
During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping Options”
section for details.

22

CRS/RMll_BTB

Ipd/G

Mll Carrier Sense Output. 
During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when RMII
mode is selected. See “Strapping Options” section for details.

23

GND

GND

Ground.

24 

VDDIO

P

Digital IO 2.5/3.3V tolerant power suppiy. 3.3V power input of voltage regulator. See “Circuit
Design Ref. for Power Supply” section for details.

25

INT#/PHYADO

Ipu/O

Management Interface (Mll) Interrupt Out. Interrupt level set by Register If, bit 9. 
During reset, latched as PHYAD[O]. See “Strapping Options” section for details.

26

LEDO/TEST

Ipu/O

Link/Activity LED Output. The external pull-down enable test mode and only used for the
factory test. Active low. 
Link/Act

Pin State

LED Definition    PHYADO

No Link

H

“Off”

Link

L

“On”

Act

-

“Toggle”

27

LED1/SPD-100/nFEF

Ipu/O

Speed LED Output Latched as SPEED (Register 0, bit 13) during power-up/reset. See
“Strapping Options” section for details. Active low.
Speed

Pin State

LED Definition

10BT

H

“Off”

100BT

L

“On”

28

LED2/

Ipu/O

Full-duplex LED Output Latched as DUPLEX (register Oh, bit 8) during power-up/reset. See
“Strapping DUPLEX Options” section for details. Active low.
Duplex

Pin State

LED Definition

Half

H

“Off”

Full

L

“On”

29

LED3/NWAYEN

Ipu/O

Collision LED Output. Latched as ANEG_EN (register Oh, bit 12) during power-up/reset See
“Strapping Options” section for details.
Collison

Pin State

LED Definition

No Collision

H

“Off”

Collision

L

“On”

30

PD#

Ipu

Power Down. 1 = Normal operation, 0 = Power-down. Active low.

31

VDDRX

P

Analog 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for details.

32

RX-

I    

Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T.

33

RX+

I 

Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T.

34

FXSD/FXEN

Ipd/O

Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The
default is “0”. See “100BT FX Mode” section for more details.

35

GND

GND

Ground.

36

GND

GND

Ground.

37

REXT

I

External resistor (6.49kW ) connects to REXT and GND.

38

VDDRCV

P

Analog 2.5V power supply. 2.5V power output of voltage regulator. See “Circuit Design Ref.
for Power Supply” section for details.

39

GND

GND

Ground.

40

TX-

O

Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.

41

TX+

O

Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.

42

VDDTX

P

Transmitter 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for
details.

43

GND

GND

Ground.

44

GND

GND

Ground.

45

XO

O

XTAL feedback: Used with XI  for Xtal application.

46

XI

Crystal Oscillator Input: Input for a crystal or an external 25MHz clock. 
If ah oscillator is used, XI connects to a 3.3V tolerant oscillator, and X2 is a no- connect .

47

VDDPLL

P

Analog PLL 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for
details.

48

RST#

Ipu

Chip Reset. Active Ipw, minimum of 50

µs pulse is required.

Pin No.

Pin Name

I/O

Description

50

1. Strap-in is latched during power-up or reset.
2.  Ipu = Input w/ internal pull-up.
Ipd/O = Input w/ internal pull-down during reset output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.

Pin No.

Pin Name

I/O

Description

6,5,  4,3

PHYAD[4:1]/RXD[0:3]

Ipd/O

PHY Address latched at power-up/reset. The default PHY address is 00001.                                                                                                 

25

PHYADO/INT# Ipu/O

9

PCS_LPBK/RXDV

Ipd/O

Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.

11

ISO/RXER

Ipd/O

Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.

21

RMII/COL

Ipd/O

Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.

22

RMII_BTBCRS

Ipd/O

Enable RMIl back-to-back mode at power-up/reset. PD (default) = Disable, PU = Enable.                          

27

SPD100/NoFEF/LED1

Ipu/O

Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) =
100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as the
Speed Support in register 4h. (If FXEN is pulled up, the latched value 0 means no Far_End
_FauIt)

28

DUPLEX/LED2

Ipu/O

Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU (default) = Full-
duplex. If Duplex is pulled up during reset, this pin is also latched as the Duplex support in
register 4h.

29

NWAYEN/LED3

Ipu/O

Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/ reset. PD
= Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.

30

 PD#

Ipu

Power-Down Enable. PU (default) =Normal operation, PD = Power-Down mode.

51

52

Note:

1. RTL (Retention Time Limited)

The marking (RTL) indicates that the Retention Time is
limited for this item.
After the discontinuation of this assembly in production,
the item will continue to be available for a specific period
of time. The retention period of availability depends on
the type of assembly and the laws governing parts and
product retention. At the end of this period, the assembly
will no longer be available.

2. Important safety notice

Components identified by the   mark indicates special
characteristics important for safety. When replacing any
of these components, only use specified manufacture's
parts.

3. The S mark means the part is one of some identical parts.

For that reason, it may be different from the installed part.

4. ISO code (Example: ABS-94HB) of the remarks column

shows quality of the material and a flame resisting grade
about plastics.

5. RESISTORS & CAPACITORS

Unless otherwise specified;
All resistors are in ohms (

Ω), k=1000Ω, M=1000kΩ

All capacitors are in MICRO FARADS (

µF), p=µµF

*Type & Wattage of Resistor