Panasonic KX-TDE0110XJ / KX-TDE0110X Service Manual ▷ View online
41
KX-TDE0110XJ / KX-TDE0110X
229
10
N2
TDM2_DR
GPIO9
I/O
Ih/Ot16 TDM2_DR: TDM Bus 2 Receive Data Input. Receive data input.
A-Law/
µ-Law PCM receive data sample from the T1/E1 Trans-
ceiver.
GPIO9: General Purpose I/O 9. Connect to pull-up if not used.
GPIO9: General Purpose I/O 9. Connect to pull-up if not used.
230
11
N3
TDM2_DX
Reserved
I/O
I/
Opsts66
Opsts66
TDM2_DX: TDM Bus 2 Transmit Data Output. Tx data output. A-
Law/
Law/
µ-Law PCM transmit data sample to the T1/E1 Transceiver.
Three-states when not shifting. TDM_DX requires a 33
Ω series
resistor, to avoid problems caused by one driver turning off, while
another driver is turning on.
Reserved
another driver is turning on.
Reserved
231
12
M4
TDM2_FS
GPIO10
I/O
Ih/Ot16 TDM2_FS: TDM Bus 2 Frame Sync. 8 kHz frame sync input from
the T1/E1 Transceiver. Each TDM bus can be connected to a dif-
ferent Frame Sync and Shift CLK.
GPIO10: General Purpose I/O 10. Internal pull-up. Leave open if
not used.
ferent Frame Sync and Shift CLK.
GPIO10: General Purpose I/O 10. Internal pull-up. Leave open if
not used.
232
13
M1
TDM3_CK
GPIO11
I/O
Ih/Ot16 TDM3_CK: TDM Bus 3 Data Shift Clock. Shift clock input (1.544
MHz - 32.768 MHz) input from the T1/E1 Transceiver. Each TDM
bus can be connected to a different Frame Sync and Shift CLK.
GPIO11: General Purpose I/O 11. Internal pull-up. Leave open if
not used.
bus can be connected to a different Frame Sync and Shift CLK.
GPIO11: General Purpose I/O 11. Internal pull-up. Leave open if
not used.
233
14
M2
TDM3_DR
PCI_REQ5#
I/O
Iu/Ots8 TDM3_DR: TDM Bus 3 Receive Data Input. Receive data input.
A-Law/
µ-Law PCM receive data sample from the T1/E1 Trans-
ceiver.
PCI_REQ5#: Request. REQ# is used to indicate to the arbiter that
this agent desires use of the bus. Connect to PCI Bus: REQ#.
PCI_REQ5#: Request. REQ# is used to indicate to the arbiter that
this agent desires use of the bus. Connect to PCI Bus: REQ#.
234
15
M3
TDM3_DX
Reserved
I/O
I/
Opsts66
Opsts66
TDM3_DX: TDM Bus 3 Transmit Data Output. Tx data output. A-
Law/
Law/
µ-Law PCM transmit data sample to the T1/E1 Transceiver.
Three-states when not shifting. TDM_DX requires a 33
Ω series
resistor, to avoid problems caused by one driver turning off, while
another driver is turning on.
Reserved
another driver is turning on.
Reserved
235
16
L4
TDM3_FS
PCI_GNT5#
I/O
Iu/Ots8 TDM3_FS: TDM Bus 3 Frame Sync. 8kHz frame sync input from
the T1/E1 Transceiver. Each TDM bus can be connected to a dif-
ferent Frame Sync and Shift CLK.
PCI_GNT5#: Grant. GNT# is used to indicate to the agent that
access to the bus has been granted. Connect to PCI Bus: GNT#.
ferent Frame Sync and Shift CLK.
PCI_GNT5#: Grant. GNT# is used to indicate to the agent that
access to the bus has been granted. Connect to PCI Bus: GNT#.
Total
Signals
Interface
Signals
Pin
UART & Extra GPIO Interface Signal
Name
Signal
Type
I/O Type
Signal Description
Pin Compatible &
Enhanced Feature
Modes
Software Selected
Features
236
1
E2
UART0_RX
GPIO16
I/O
Ihu/Ot16 UART0_RX: UART Receive Data. Internal pull-up. Useful
software debug port. Recommend connection to a test point
for debug.
GPIO16: General Purpose I/O 16. Internal pull-up. Leave
open if not used.
for debug.
GPIO16: General Purpose I/O 16. Internal pull-up. Leave
open if not used.
237
2
E4
UART0_TX
GPIO17
I/O
Ihu/Ot16 UART0_TX: UART Transmit Data. Useful software debug
port. Recommend connection to a test point for debug.
GPIO17: General Purpose I/O 17. Internal pull-up. Leave
open if not used.
GPIO17: General Purpose I/O 17. Internal pull-up. Leave
open if not used.
238
3
Y2
Reserved
UART1_RX
I
Id
Reserved. Internal pull-down. Leave open.
UART1_RX: UART Receive Data. Internal pull-up. Useful
software debug port. Recommend connection to a test point
for debug.
UART1_RX: UART Receive Data. Internal pull-up. Useful
software debug port. Recommend connection to a test point
for debug.
239
4
AA1
Reserved
UART1_TX
O
Id/Ot8
Reserved: Internal pull-down. Leave open.
UART1_TX: UART Transmit Data. Useful software debug
port. Recommend connection to a test point for debug.
UART1_TX: UART Transmit Data. Useful software debug
port. Recommend connection to a test point for debug.
Total
Signals
Interface
Signals
Pin
TDM Bus & Extra GPIO Interface
Signal Name
Signal
Type
I/O Type
Signal Description
Pin Compatible
& Enhanced
Feature Mode
S/W Selected
Features
42
KX-TDE0110XJ / KX-TDE0110X
Total
Signals
Interface
Signals
Pin
GPIO, JTAG, Configuration, PLL, and
Test Interface Signal Name
Signal
Type
I/O Type
Signal Description
Pin Compatible &
Enhanced Feature
Modes
Software Selected
Features
GPIO Interface
240
1
A1
GPIO0
Ihu/Ot16 General Purpose I/O 0. Internal pull-up. Pull-down option
and connection to a test point is recommended. Leave open
if not used.
Refer to M82xxx GPIO Usage App Note (82xxx-APP-010)
for information on GPIO allocation.
if not used.
Refer to M82xxx GPIO Usage App Note (82xxx-APP-010)
for information on GPIO allocation.
241
2
A2
GPIO1
I/O
Ihu/Ot16 General Purpose I/O 1. Same as GPIO0.
242
3
B3
GPIO2
I/O
Ihu/Ot16 General Purpose I/O 2. Same as GPIO0
243
4
C3
GPIO3
I/O
Ihu/Ot16 General Purpose I/O 3. Same as GPIO0
244
5
A4
GPIO4
I/O
Ihu/Ot16 General Purpose I/O 4. Same as GPIO0.
245
6
D3
GPIO5
I/O
Ihu/Ot16 General Purpose I/O 5. Same as GPIO0
246
7
C4
GPIO6
I/O
Ihu/Ot16 General Purpose I/O 6. Same as GPIO0
247
8
B4
GPIO7
I/O
Ihu/Ot16 General Purpose I/O 7. Same as GPIO0.
For Master Mode (i.e. Host is internal CSP ARM core) - MSP
Initialization. If standard code is used for the M825xx(2)
device, and it is operating with the CSP controlling the sys-
tem (no external host CPU), then GPIO7 will be dedicated to
supporting CSP re-start of the MSP, and will not be available
as an IO. In this case, leave open, no connect.
For Slave Mode (i.e. Host is an external uP Controller) - Boot
Loader Select. Selects the boot loader to use during power-
on reset initialization.
High = PCI/uP Parallel Bus Host Interface Mode Boot
Loader.
Low = Ethernet Interface Mode Boot Loader.
Initialization. If standard code is used for the M825xx(2)
device, and it is operating with the CSP controlling the sys-
tem (no external host CPU), then GPIO7 will be dedicated to
supporting CSP re-start of the MSP, and will not be available
as an IO. In this case, leave open, no connect.
For Slave Mode (i.e. Host is an external uP Controller) - Boot
Loader Select. Selects the boot loader to use during power-
on reset initialization.
High = PCI/uP Parallel Bus Host Interface Mode Boot
Loader.
Low = Ethernet Interface Mode Boot Loader.
JTAG Interface
248
1
W3
TCK
I
Ihu
JTAG Test Clock. This is the JTAG clock signal. This pin has
an internal pull-up, and it conforms to IEEE 1149.1 JTAG
specification.
an internal pull-up, and it conforms to IEEE 1149.1 JTAG
specification.
249
2
Y4
TDI
I
Ihu
JTAG Test Input Data. This is the boundary scan serial input
signal, and it is shifted in on the rising edge of TCK. The pin
has an internal pull-up, and it conforms to IEEE 1149.1 JTAG
specification.
signal, and it is shifted in on the rising edge of TCK. The pin
has an internal pull-up, and it conforms to IEEE 1149.1 JTAG
specification.
250
3
Y3
TDO
O
Ots8
JTAG Test Output Data. This is the three-stateable boundary
scan data output signal, and it is shifted out on the falling
edge of TCK. It conforms to IEEE 1149.1 JTAG specification.
scan data output signal, and it is shifted out on the falling
edge of TCK. It conforms to IEEE 1149.1 JTAG specification.
251
4
W1
TMS
I
Ihu
JTAG Test Mode Select. This is the control signal to the TAP
controller. This pin has an internal pull-up, and it conforms to
IEEE 1149.1 JTAG specification.
controller. This pin has an internal pull-up, and it conforms to
IEEE 1149.1 JTAG specification.
252
5
W5
TRST#
I
Ihu
JTAG Test Reset. A low signal forces the TAP controller into
a logic reset state. TRST# must be open (i.e., unconnected)
for normal (non-test) operation. This pin has an internal pull-
up, and it conforms to IEEE 1149.1 JTAG specification.
a logic reset state. TRST# must be open (i.e., unconnected)
for normal (non-test) operation. This pin has an internal pull-
up, and it conforms to IEEE 1149.1 JTAG specification.
253
6
B1
JTAG_MODE
I
Ihu
JTAG Mode Select. Input with internal pull-up. To hold low,
connect to 100
connect to 100
Ω pull-down to GND.
Logic Low (0) = ARM only (for customer ICE)
Logic High (1) = ARM + SPU (for Mindspeed SPU debug)
Logic High (1) = ARM + SPU (for Mindspeed SPU debug)
Configuration, PLL, and Test Interface
254
1
U21
PLL_REFCLK
I
Ih
Reference Clock In. Connect to an external 10.000 MHz
clock.
clock.
255
2
U20
RESET#
I
Ih
Reset. Active low input asserted to initialize the M825xx(2)
device, including PCI-specific registers, sequencers, and
signals to a consistent reset state. Customers must imple-
ment a Host controllable method to activate the Hardware
Reset pin on each M825xx(2) device. This is required for all
M825xx(2) designs. The M825xx(2) Hardware Reset pin
must be held in the active (logic low) state for at least 2 ms,
for valid Reset operation. All clocks (REFCLK, PCI_CLK,
and TDM_CK) must be running for the M825xx(2) device to
perform a valid Reset operation.
device, including PCI-specific registers, sequencers, and
signals to a consistent reset state. Customers must imple-
ment a Host controllable method to activate the Hardware
Reset pin on each M825xx(2) device. This is required for all
M825xx(2) designs. The M825xx(2) Hardware Reset pin
must be held in the active (logic low) state for at least 2 ms,
for valid Reset operation. All clocks (REFCLK, PCI_CLK,
and TDM_CK) must be running for the M825xx(2) device to
perform a valid Reset operation.
256
3
C21
OPMODE1
I
Iu
Operation Mode 1. Used to select device configuration. Inter-
nal pull-up.
nal pull-up.
257
4
B22
OPMODE0
I
Iu
Operation Mode 0. Used to select device configuration. Inter-
nal pull-up.
nal pull-up.
43
KX-TDE0110XJ / KX-TDE0110X
258
5
C2
EROM#
I
Iu
External Boot ROM. Used to enable external Boot ROM.
Internal pull-up.
Internal pull-up.
259
6
B20
IRAMBOOT#
I
Iu/Ot4
IRAM Boot. Used to select device configuration. Internal pull-
up. Leave open.
up. Leave open.
260
7
C22
PLLBYPASS#
I
Iu
PLL Bypass. Used for factory device test only. Internal pull-
up. Leave open.
up. Leave open.
261
8
Y21
BSCANMODE#
I
Iu
Boundary Scan Mode. Low input configures the JTAG port
for boundary scan. High input configures the JTAG port as a
debug port. Internal pull-up.
NOTE: For normal operation, BSCANMODE# must be high
(default state due to internal pull-up).
for boundary scan. High input configures the JTAG port as a
debug port. Internal pull-up.
NOTE: For normal operation, BSCANMODE# must be high
(default state due to internal pull-up).
262
9
W21
BISR#
I
Iu
Built In Self Repair Enable. Used for factory device test only.
Internal pull-up. Leave open.
Internal pull-up. Leave open.
263
10
B2
FUSE
I
Iu
Fuse Usage Enable. Used for factory device test only. Inter-
nal pull-up. Leave open.
nal pull-up. Leave open.
264
11
A22
TRISTATE#
I
Iu
Three-state All Outputs. Low input three-states all outputs.
High input enables normal output drive states. May be used
for board manufacturing test. Internal pull-up.
High input enables normal output drive states. May be used
for board manufacturing test. Internal pull-up.
265
1
T4
Reserved
I
Iu/Ots8 Reserved. Internal pull-up. Leave open.
266
2
T2
Reserved
I
Iu/Ots8 Reserved. Internal pull-up. Leave open.
267
3
T3
Reserved
I
Iu/Ots8 Reserved. Internal pull-up. Leave open.
268
4
T1
Reserved
O
Iu/Ots8 Reserved. Output. Leave open.
Extra GPIO Mode
269
1
D21
Reserved
GPIO18
I
I/Ots8
General Purpose I/O. Connect to pull-up if not used.
270
2
D1
Reserved
Reserved
I/O
USB
Reserved. Connect to 15k
Ω pull-down to GND.
271
3
C1
Reserved
Reserved
I/O
USB
Reserved. Connect to 15k
Ω pull-down to GND.
272
4
D22
Reserved
GPIO19
I
I/Ots8
General Purpose I/O. Connect to pull-up if not used.
273
5
E3
Reserved
Reserved
I/O
USB
Reserved. Connect to 15k
Ω pull-down to GND.
274
6
D2
Reserved
Reserved
I/O
USB
Reserved. Connect to 15k
Ω pull-down to GND.
Total
Signals
Interface
Signals
Pin
SPI Bus & Extra GPIO Interface Signal
Name
Signal
Type
I/O Type
Signal Description
Pin Compatible
Mode
Enhanced
Feature Mode
Software
Selected
Features
Selected
Features
275
1
Y1
Reserved
SPI_SCLK
SPI_SCLK
I/O
I/Ots8
Reserved:
SPI_SCLK: SPI Serial Clock Output
SPI_SCLK: SPI Serial Clock Output
276
2
V4
Reserved
PCI_GNT4#
SPI_TXD
I/O
I/Ots8
Reserved.
PCI_GNT4#: Grant. GNT# is used to indicate to the
agent that access to the bus has been granted. Con-
nect to PCI Bus: GNT#.
SPI_TXD: SPI Transmit Data Output.
PCI_GNT4#: Grant. GNT# is used to indicate to the
agent that access to the bus has been granted. Con-
nect to PCI Bus: GNT#.
SPI_TXD: SPI Transmit Data Output.
277
3
V2
Reserved
PCI_REQ4#
SPI_RXD
I/O
I/Ots8
Reserved.
PCI_REQ4#: Request. REQ# is used to indicate to the
arbiter that this agent desires use of the bus. Connect
to PCI Bus: REQ#.
SPI_RXD: SPI Receive Data Input
PCI_REQ4#: Request. REQ# is used to indicate to the
arbiter that this agent desires use of the bus. Connect
to PCI Bus: REQ#.
SPI_RXD: SPI Receive Data Input
278
4
V3
Reserved
GPIO12
SPI_SS0#
I/O
I/Ots8
Reserved.
GPIO12: General Purpose I/O 12. Connect to pull-up
if not used.
SPI_SS0#: SPI Slave Select 0 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
GPIO12: General Purpose I/O 12. Connect to pull-up
if not used.
SPI_SS0#: SPI Slave Select 0 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
279
5
V1
Reserved
GPIO13
SPI_SS1#
I/O
I/Ots8
Reserved.
GPIO13: General Purpose I/O 13
Connect to pull-up if not used.
SPI_SS1#: SPI Slave Select 1 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
GPIO13: General Purpose I/O 13
Connect to pull-up if not used.
SPI_SS1#: SPI Slave Select 1 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
Total
Signals
Interface
Signals
Pin
GPIO, JTAG, Configuration, PLL, and
Test Interface Signal Name
Signal
Type
I/O Type
Signal Description
Pin Compatible &
Enhanced Feature
Modes
Software Selected
Features
44
KX-TDE0110XJ / KX-TDE0110X
280
6
U4
Reserved
GPIO14
SPI_SS2#
I/O
I/Ots8
Reserved.
GPIO14: General Purpose I/O 14. Connect to pull-up
if not used.
SPI_SS2#: SPI Slave Select 2 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
GPIO14: General Purpose I/O 14. Connect to pull-up
if not used.
SPI_SS2#: SPI Slave Select 2 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
281
7
U2
Reserved
GPIO15
SPI_SS3#
I/O
I/Ots8
Reserved.
GPIO15: General Purpose I/O 15. Connect to pull-up
if not used.
SPI_SS3#: SPI Slave Select 3 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
GPIO15: General Purpose I/O 15. Connect to pull-up
if not used.
SPI_SS3#: SPI Slave Select 3 Output can be used
directly as a Chip Select, or SS[3:0] can be decoded
to create 16 Chip Selects.
Reserved
282
8
C19
Reserved
Reserved
I/O
I/Ots8
Reserved. Leave open.
283
9
C20
Reserved
Reserved
I/O
I/Ots8
Reserved. Leave open.
284
10
U3
Reserved
Reserved
I/O
I/Ots8
Reserved. Leave open.
285
11
U1
Reserved
Reserved
I/O
I/Ots8
Reserved. Leave open.
Total
Signals
Interface
Signals
Pin
Power (VDD) Interface
All Modes
Signal
Type
I/O Type
Signal Description
1.2 VDC Vcore
286
1
F6
VDD
P
PWR
Core Supply Voltage. Connect to +1.2 VDC. Provide decoupling capacitors
distributed uniformly among the pins and located as close to the device as
possible. For recommended capacitors refer to the DC Power Stability Prod-
uct Bulletin (82xxx-PBD-001).
distributed uniformly among the pins and located as close to the device as
possible. For recommended capacitors refer to the DC Power Stability Prod-
uct Bulletin (82xxx-PBD-001).
287
2
F7
VDD
P
PWR
Same as above.
288
3
F8
VDD
P
PWR
Same as above.
289
4
F9
VDD
P
PWR
Same as above.
290
5
F10
VDD
P
PWR
Same as above.
291
6
F11
VDD
P
PWR
Same as above.
292
7
F12
VDD
P
PWR
Same as above.
293
8
F13
VDD
P
PWR
Same as above.
294
9
F14
VDD
P
PWR
Same as above.
295
10
F15
VDD
P
PWR
Same as above.
296
11
F16
VDD
P
PWR
Same as above.
297
12
F17
VDD
P
PWR
Same as above.
298
13
G6
VDD
P
PWR
Same as above.
299
14
G7
VDD
P
PWR
Same as above.
300
15
G8
VDD
P
PWR
Same as above.
301
16
G9
VDD
P
PWR
Same as above.
302
17
G10
VDD
P
PWR
Same as above.
303
18
G11
VDD
P
PWR
Same as above.
304
19
G12
VDD
P
PWR
Same as above.
305
20
G13
VDD
P
PWR
Same as above.
306
21
G14
VDD
P
PWR
Same as above.
307
22
G15
VDD
P
PWR
Same as above.
308
23
G16
VDD
P
PWR
Same as above.
309
24
G17
VDD
P
PWR
Same as above.
310
25
H6
VDD
P
PWR
Same as above.
311
26
H7
VDD
P
PWR
Same as above.
312
27
H16
VDD
P
PWR
Same as above.
313
28
H17
VDD
P
PWR
Same as above.
314
29
J6
VDD
P
PWR
Same as above.
315
30
J7
VDD
P
PWR
Same as above.
316
31
J16
VDD
P
PWR
Same as above.
317
32
J17
VDD
P
PWR
Same as above.
318
33
K6
VDD
P
PWR
Same as above.
319
34
K7
VDD
P
PWR
Same as above.
320
35
K16
VDD
P
PWR
Same as above.
321
36
K17
VDD
P
PWR
Same as above.
322
37
L6
VDD
P
PWR
Same as above.
323
38
L7
VDD
P
PWR
Same as above.
324
39
L16
VDD
P
PWR
Same as above.
Total
Signals
Interface
Signals
Pin
SPI Bus & Extra GPIO Interface Signal
Name
Signal
Type
I/O Type
Signal Description
Pin Compatible
Mode
Enhanced
Feature Mode
Software
Selected
Features
Selected
Features
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