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37

182

24

A9

PUO_PRTY SDR_DATA04 Reserved

I/O

I/
Opsts66

PUO_PRTY: Master Mode Parity (OB_PRTY). Bus par-
ity signal indicates the parity calculated over the whole
PUO_DAT [15:0] bus. Both even and odd parity is sup-
ported.
Slave Mode Parity (OB_PRTY). Bus parity signal indi-
cates the parity calculated over the whole PUO_DAT
[15:0] bus. Both even and odd parity is supported.
SDR_DATA04: Same as SDR_DATA00.
Reserved. Leave open.

183

25

B10

PUO_SOCP SDR_DATA12 Reserved

I/O

I/
Opsts66

PUO_SOCP: Master Mode Start Of Cell or Packet
(TLO_SOCP). Start of Cell or Packet indicates the first
word of a cell or packet. PUO_SOCP is asserted at the
beginning of every cell or packet.
Slave Mode Start Of Cell or Packet (RPO_SOCP). Start
of Cell or Packet indicates the first word of a cell or
packet. PUO_SOCP is asserted at the beginning of
every cell or packet. PUO_SCOP is tri-stated by RxENB.
SDR_DATA12: Same as SDR_DATA00.
Reserved. Leave open.

184

26

A10

PUO_EOP

SDR_DATA05 Reserved

I/O

I/
Opsts66

PUO_EOP: End of packet. Not used in Utopia Mode.
SDR_DATA05: Same as SDR_DATA00.
Reserved. Leave open.

185

27

C10

PUO_MOD

SDR_DATA13 Reserved

I/O

I/
Opsts66

PUO_MOD: Modulo. Not used in Utopia Mode.
SDR_DATA13: Same as SDR_DATA00.
Reserved. Leave open.

186

28

D10

PUO_ERR

SDR_DATA06 Reserved

I/O

I/
Opsts66

PUO_ERR: Error. Not used in Utopia Mode.
SDR_DATA06: Same as SDR_DATA00.
Reserved. Leave open.

187

29

A11

PUO_CTRL1 SDR_DATA14 Reserved

I/O

I/
Opsts66

PUO_CTRL1: Master Mode Multifunction signal
(TLO_ENB). In UTOPIA Master Mode, used as
TLO_ENB signal.
Slave Mode Multifunction signal (RPO_EMPTY_CLAV).
In UTOPIA Slave Mode, used as RPO_EMPTY_CLAV
signal.
SDR_DATA14: Same as SDR_DATA00.
Reserved. Leave open.

188

30

B11

PUO_CTRL2 SDR_DATA07 Reserved

I/O

I/
Opsts66

PUO_CTRL2: Master Mode Multifunction signal. Not
used in UTOPIA Master Mode.
Slave Mode Multifunction signal (RPI_ENB). In UTOPIA
Slave Mode, used as RPI_ENB signal.
SDR_DATA07: Same as SDR_DATA00.
Reserved. Leave open.

189

31

C11

PUO_CTRL3 SDR_DATA15 Reserved

I/O

I/
Opsts66

PUO_CTRL3: Master Mode Multifunction signal
(TLI_FULL_CLAV). In UTOPIA Master Mode, used as
TLI_FULL_CLAV signal.
Slave Mode Multifunction signal. Not used in UTOPIA
Slave Mode.
SDR_DATA15: Same as SDR_DATA00.
Reserved. Leave open.

190

32

A12

PUI_CLK

SDR_CLK

Reserved

O

I/Ot16

PUI_CLK: Master Mode Data transfer / synchronization
clock (RLI_CLK). Clock is used to synchronize data
transfers on the bus, and the rate can be 25 MHz, 33
MHz, or 50 MHz.
Slave Mode Data transfer / synchronization clock
(TPI_CLK). Clock is used to synchronize data transfers
on the bus, and the rate can be 25 MHz, 33 MHz, or
50MHz.
SDR_CLK: SDRAM Clock Out. SDRAM clock output.
Connect to SDRAM CLK. Note: SDR_CLK has 16 mA
current drive, and no slew rate control. It is recom-
mended to include a series terminating resistor at the
output of this pin to avoid undershoot and overshoot.
Reserved. Leave open.

Total 

Signals

Interface 

Signals

Pin

Utopia & 2nd SDRAM Interface Signal 

Name

Signal 

Type

I/O Type

Signal Description

Pin 

Compatible 

Mode with 

Utopia Bus

Enhanced 

Feature Mode 

with Second 

SDRAM 

Interface

Enhanced 

Feature 

Mode with 

Extra GPIO

38

191

33

B18

PUI_ADR0

SDR_A00

Reserved

O

I/
Opsts66

PUI_ADR0: Master Mode Address (RLO_ADR[4:0]).
Address bus used to select a device (or port) on the bus.
Note that address 0x1F is the null-PHY address and
shall not be assigned to any port on the bus.
Slave Mode Address (TPI_ADR[4:0]). Address bus used
to select a device (or port) on the bus.
Note that address 0x1F is the null-PHY address and
shall not be assigned to any port on the bus.
SDR_A00: Second SDRAM Bus Address [00]. Address
output. Connect to SDRAM address input.
Reserved. Leave open.

192

34

A20

PUI_ADR1

SDR_A01

Reserved

O

I/
Opsts66

PUI_ADR1: Same as PUI_ADR0.
SDR_A01: Same as SDR_A00.
Reserved. Leave open.

193

35

A19

PUI_ADR2

SDR_A02

Reserved

O

I/
Opsts66

PUI_ADR2: Same as PUI_ADR0.
SDR_A02: Same as SDR_A00.
Reserved. Leave open.

194

36

C18

PUI_ADR3

SDR_A03

Reserved

O

I/
Opsts66

PUI_ADR3: Same as PUI_ADR0.
SDR_A03: Same as SDR_A00.
Reserved. Leave open.

195

37

B19

PUI_ADR4

SDR_A04

Reserved

O

I/
Opsts66

PUI_ADR4: Same as PUI_ADR0.
SDR_A04: Same as SDR_A00.
Reserved. Leave open.

196

38

B14

PUI_DAT00

SDR_DATA20 Reserved

I/O

I/
Opsts66

PUI_DAT00: Master Mode Data signal (IB_DAT). Packet
Data Bus carries the packet octets. Data must be in big
endian order. Bits are in the following order: 15, 14 ... 8,
7, 6 ... 1, 0.
Slave Mode Data signal (IB_DAT). Packet Data Bus car-
ries the packet octets. Data must be in big endian order.
Bits are in the following order: 15, 14 ... 8, 7, 6 ... 1, 0.
SDR_DATA20: Same as SDR_DATA00.
Reserved. Leave open.

197

39

A15

PUI_DAT01

SDR_DATA27 Reserved

I/O

I/
Opsts66

PUI_DAT01: Same as PUI_DAT00.
SDR_DATA27: Same as SDR_DATA00.
Reserved. Leave open.

198

40

C14

PUI_DAT02

SDR_DATA21 Reserved

I/O

I/
Opsts66

PUI_DAT02: Same as PUI_DAT00.
SDR_DATA21: Same as SDR_DATA00.
Reserved. Leave open.

199

41

D14

PUI_DAT03

SDR_DATA26 Reserved

I/O

I/
Opsts66

PUI_DAT03: Same as PUI_DAT00.
SDR_DATA26: Same as SDR_DATA00.
Reserved. Leave open.

200

42

B15

PUI_DAT04

SDR_DATA22 Reserved

I/O

I/
Opsts66

PUI_DAT04: Same as PUI_DAT00.
SDR_DATA22: Same as SDR_DATA00.
Reserved. Leave open.

201

43

A16

PUI_DAT05

SDR_DATA25 Reserved

I/O

I/
Opsts66

PUI_DAT05: Same as PUI_DAT00.
SDR_DATA25: Same as SDR_DATA00.
Reserved. Leave open.

202

44

C15

PUI_DAT06

SDR_CLKE

Reserved

O

I/
Opsts66

PUI_DAT06: Same as PUI_DAT00.
SDR_CLKE: SDRAM Clock Enable. SDRAM clock
enable output. Not used. 
Connect SDRAM CKE to a pull-up resistor.
Reserved. Leave open.

203

45

D15

PUI_DAT07

SDR_DATA23 Reserved

I/O

I/
Opsts66

PUI_DAT07: Same as PUI_DAT00.
SDR_DATA23: SDRAM Bus Data [31:00].
Connect SDR_DATA[31:00] to SDRAM D[31:00],
respectively.
Reserved. Leave open.

204

46

B16

PUI_DAT08

SDR_DATA24 GPIO24

I/O

I/
Opsts66

PUI_DAT08: Same as PUI_DAT00.
SDR_DATA24: Same as SDR_DATA00.
GPIO24: General Purpose I/O 24. Connect to pull-up if
not used.

Total 

Signals

Interface 

Signals

Pin

Utopia & 2nd SDRAM Interface Signal 

Name

Signal 

Type

I/O Type

Signal Description

Pin 

Compatible 

Mode with 

Utopia Bus

Enhanced 

Feature Mode 

with Second 

SDRAM 

Interface

Enhanced 

Feature 

Mode with 

Extra GPIO

39

205

47

A17

PUI_DAT09

SDR_DQM2

GPIO25

O

I/
Opsts66

PUI_DAT09: Same as PUI_DAT00.
SDR_DQM2: Same as SDR_DQM0.
GPIO25: General Purpose I/O 25. Connect to pull-up if
not used.

206

48

C16

PUI_DAT10

SDR_DQM3

GPIO26

O

I/
Opsts66

PUI_DAT10: Same as PUI_DAT00.
SDR_DQM3: Same as SDR_DQM0.
GPIO26: General Purpose I/O 26. Connect to pull-up if
not used.

207

49

D16

PUI_DAT11

SDR_CS0#

GPIO27

O

I/
Opsts66

PUI_DAT11: Same as PUI_DAT00.
SDR_CS0#: SDRAM Chip Select 0. Active low SDRAM
Chip Select 0. Connect to SDRAM CS# pin.
NOTE: SDRAM device chip select pin must be con-
nected to SDR_CS0# (i.e. it must not be connected to
ground)
GPIO27: General Purpose I/O 27. Connect to pull-up if
not used.

208

50

B17

PUI_DAT12

SDR_A05

GPIO28

O

I/
Opsts66

PUI_DAT12: Same as PUI_DAT00.
SDR_A05: Same as SDR_A00.
GPIO28: General Purpose I/O 28. Connect to pull-up if
not used.

209

51

A18

PUI_DAT13

SDR_A06

GPIO29

O

I/
Opsts66

PUI_DAT13: Same as PUI_DAT00.
SDR_A06: Same as SDR_A00.
GPIO29: General Purpose I/O 29. Connect to pull-up if
not used.

210

52

C17

PUI_DAT14

SDR_A07

GPIO30

O

I/
Opsts66

PUI_DAT14: Same as PUI_DAT00.
SDR_A07: Same as SDR_A00.
GPIO30: General Purpose I/O 30. Connect to pull-up if
not used.

211

53

D17

PUI_DAT15

SDR_A08

GPIO31

O

I/
Opsts66

PUI_DAT15: Same as PUI_DAT00.
SDR_A08: Same as SDR_A00.
GPIO31: General Purpose I/O 31. Connect to pull-up if
not used.

212

54

D13

PUI_PRTY

SDR_DATA28 Reserved

I/O

I/
Opsts66

PUI_PRTY: Master Mode Parity (IB_PRTY). Bus parity
signal indicates the parity calculated over the whole
PUO_DAT [15:0] bus. Both even and odd parity is sup-
ported.
Slave Mode Parity (IB_PRTY). Bus parity signal indi-
cates the parity calculated over the whole PUO_DAT
[15:0] bus. Both even and odd parity is supported.
SDR_DATA28: Same as SDR_DATA00.
Reserved. Leave open.

213

55

C13

PUI_SOCP

SDR_DATA19 Reserved

I/O

I/
Opsts66

PUI_SOCP: Master Mode Start Of Cell or Packet
(RLI_SOCP). Start of Cell or Packet indicates the first
word of a cell or packet. PUO_SOCP is asserted at the
beginning of every cell or packet.
Slave Mode Start Of Cell or Packet (TPI_SOCP). Start of
Cell or Packet indicates the first word of a cell or packet.
PUO_SOCP is asserted at the beginning of every cell or
packet. PUO_SCOP is tri-stated by RxENB.
SDR_DATA19: Same as SDR_DATA00.
Reserved. Leave open.

214

56

A14

PUI_EOP

SDR_DATA29 Reserved

I/O

I/
Opsts66

PUI_EOP: End of packet. Not used in Utopia Mode.
SDR_DATA29: Same as SDR_DATA00.
Reserved. Leave open.

215

57

B13

PUI_MOD

SDR_DATA18 Reserved

I/O

I/
Opsts66

PUI_MOD: Modulo. Not used in Utopia Mode.
SDR_DATA18: Same as SDR_DATA00.
Reserved. Leave open.

216

58

D12

PUI_ERR

SDR_DATA30 Reserved

I/O

I/
Opsts66

PUI_ERR: Error. Not used in Utopia Mode.
SDR_DATA30: Same as SDR_DATA00.
Reserved. Leave open.

Total 

Signals

Interface 

Signals

Pin

Utopia & 2nd SDRAM Interface Signal 

Name

Signal 

Type

I/O Type

Signal Description

Pin 

Compatible 

Mode with 

Utopia Bus

Enhanced 

Feature Mode 

with Second 

SDRAM 

Interface

Enhanced 

Feature 

Mode with 

Extra GPIO

40

217

59

B12

PUI_CTRL1 SDR_DATA16 Reserved

I/O

I/
Opsts66

PUI_CTRL1: Master Mode Multifunction signal
(RLI_EMPTY_CLAV). In UTOPIA Master Mode, used as
RLI_EMPTY_CLAV signal.
Slave Mode Multifunction signal (TPI_ENB). In UTOPIA
Slave Mode, used as TPI_ENB signal.
SDR_DATA16: Same as SDR_DATA00.
Reserved. Leave open.

218

60

C12

PUI_CTRL2 SDR_DATA31 Reserved

I/O

I/
Opsts66

PUI_CTRL2: Master Mode Multifunction signal
(RLO_ENB). In UTOPIA Master Mode, used as
RLO_ENB signal.
Slave Mode Multifunction signal. Not used in UTOPIA
Slave Mode.
SDR_DATA31: Same as SDR_DATA00.
Reserved. Leave open.

219

61

A13

PUI_CTRL3 SDR_DATA17 Reserved

I/O

I/
Opsts66

PUI_CTRL3: Master Mode Multifunction signal. Not
used in UTOPIA Master Mode.
Slave Mode Multifunction signal (TPO_FULL_CLAV). In
UTOPIA Slave Mode, used as TPO_FULL_CLAV signal.
SDR_DATA17: Same as SDR_DATA00.
Reserved. Leave open.

Total 

Signals

Interface 

Signals

Pin

Utopia & 2nd SDRAM Interface Signal 

Name

Signal 

Type

I/O Type

Signal Description

Pin 

Compatible 

Mode with 

Utopia Bus

Enhanced 

Feature Mode 

with Second 

SDRAM 

Interface

Enhanced 

Feature 

Mode with 

Extra GPIO

Total 

Signals

Interface 

Signals

Pin

TDM Bus & Extra GPIO Interface 

Signal Name

Signal 

Type

I/O Type

Signal Description

Pin Compatible 

& Enhanced 

Feature Mode

S/W Selected 

Features

220

1

R2

TDM0_CK

TDM0_CK

I

I/
Opsts66

TDM Bus 0 Data Shift Clock. Shift clock input (1.544 MHz - 32.768
MHz) input from the T1/E1 Transceiver. Each TDM bus can be
connected to a different Frame Sync and Shift CLK.
Note: TDM0_CK must be provided when the TDM interface is
unused.

221

2

R1

TDM0_DR

TDM0_DR

I

I/
Opsts66

TDM Bus 0 Receive Data Input. Receive data input. A-Law/

µ-Law

PCM receive data sample from the T1/E1 Transceiver.

222

3

R3

TDM0_DX

TDM0_DX

O

I/
Opsts66

TDM Bus 0 Transmit Data Output. Tx data output. A-Law/

µ-Law

PCM transmit data sample to the T1/E1 Transceiver. Three-states
when not shifting. TDM_DX requires a 33

Ω series resistor, to

avoid problems caused by one driver turning off, while another
driver is turning on.

223

4

P4

TDM0_FS

TDM0_FS

I

I/
Opsts66

TDM Bus 0 Frame Sync. 8kHz frame sync input from the T1/E1
Transceiver. Each TDM bus can be connected to a different
Frame Sync and Shift CLK.
Note: TDM0_FS must be provided when the TDM interface is
unused.

224

5

P1

TDM1_CK

TDM1_CK

I

Ih

TDM Bus 1 Data Shift Clock. Shift clock input (1.544 MHz - 32.768
MHz) input from the T1/E1 Transceiver. Each TDM bus can be
connected to a different Frame Sync and Shift CLK.

225

6

P2

TDM1_DR

TDM1_DR

I

Ih

TDM Bus 1 Receive Data Input. Receive data input. A-Law/

µ-Law

PCM receive data sample from the T1/E1 Transceiver.

226

7

P3

TDM1_DX

TDM1_DX

O

I/
Opsts66

TDM Bus 1 Transmit Data Output. Tx data output. A-Law/

µ-Law

PCM transmit data sample to the T1/E1 Transceiver. Three-states
when not shifting. TDM_DX requires a 33

Ω series resistor, to

avoid problems caused by one driver turning off, while another
driver is turning on.

227

8

N4

TDM1_FS

TDM1_FS

I

Ih

TDM Bus 1 Frame Sync. 8kHz frame sync input from the T1/E1
Transceiver. Each TDM bus can be connected to a different
Frame Sync and Shift CLK.

228

9

N1

TDM2_CK

GPIO8

I/O

Ih/Ot16 TDM2_CK: TDM Bus 2 Data Shift Clock. Shift clock input (1.544

MHz - 32.768 MHz) input from the T1/E1 Transceiver. Each TDM
bus can be connected to a different Frame Sync and Shift CLK.
GPIO8: General Purpose I/O 8. Connect to pull-up if not used.