Panasonic KX-TDE0110XJ / KX-TDE0110X Service Manual ▷ View online
33
KX-TDE0110XJ / KX-TDE0110X
139
6
H2
RMII_100Mbps
Mode#
Reserved
MII_RXD3
I
Id/Ot4
RMII_100Mbps Mode#: 100Mbps Mode 0 (Low) =
100 Mbps Mode (default, internal pull-down)
1 (High) = 10 Mbps Mode
Reserved: Internal pull-down. Leave open if not
used.
MII_RXD3: Same as MII_RXD2.
100 Mbps Mode (default, internal pull-down)
1 (High) = 10 Mbps Mode
Reserved: Internal pull-down. Leave open if not
used.
MII_RXD3: Same as MII_RXD2.
140
7
K4
RMII_REFCLK S3MII0_RX_C
LK
MII_RX_CLK
I
Ihu
RMII_REFCLK: Reference Clock: The
RMII_REFCLK frequency is 50 MHz ± 100 ppm with
a duty cycle between 35% and 65% inclusive. For
detailed information, refer to IEEE 802.3.
S3MII0_RX_CLK: Receive Clock: Synchronous
clock for receive data. S3MII0_RX_CLK is sourced
by the PHY or an external source. The
S3MII0_RX_CLK frequency for SMII is 125 MHz ±
100 ppm with a duty cycle between 35% and 65%
inclusive. For detailed information, refer to IEEE
802.3.
MII_RX_CLK: Receive Clock: Synchronous clock for
receive data. MII_RX_CLK is sourced by the PHY or
an external source. The MII_RX_CLK frequency is
25MHz ± 100ppm with a duty cycle between 35%
and 65% inclusive. For detailed information, refer to
IEEE 802.3.
RMII_REFCLK frequency is 50 MHz ± 100 ppm with
a duty cycle between 35% and 65% inclusive. For
detailed information, refer to IEEE 802.3.
S3MII0_RX_CLK: Receive Clock: Synchronous
clock for receive data. S3MII0_RX_CLK is sourced
by the PHY or an external source. The
S3MII0_RX_CLK frequency for SMII is 125 MHz ±
100 ppm with a duty cycle between 35% and 65%
inclusive. For detailed information, refer to IEEE
802.3.
MII_RX_CLK: Receive Clock: Synchronous clock for
receive data. MII_RX_CLK is sourced by the PHY or
an external source. The MII_RX_CLK frequency is
25MHz ± 100ppm with a duty cycle between 35%
and 65% inclusive. For detailed information, refer to
IEEE 802.3.
141
8
L3
RMII_CRS_DV Reserved
MII_RX_DV
I
Id
RMII_CRS_DV/ MII_RX_DV: Receive Data Valid.
DV shall be asserted by the PHY when the receive
medium is not idle. For detailed information, refer to
IEEE 802.3.
Reserved: Reserved in S3MII Mode.
DV shall be asserted by the PHY when the receive
medium is not idle. For detailed information, refer to
IEEE 802.3.
Reserved: Reserved in S3MII Mode.
142
9
K1
RMII_RX_ER
S3MII0_RXSY
NC
NC
MII_RX_ER
I
I/Ot4
RMII_RX_ER: Receive Error. ER shall be asserted
by the PHY when an error is detected during frame
reception. Connect to Ethernet PHY Rx_ER.
S3MII0_RXSYNC: Rx Sync
MII_RX_ER: Receive Error. ER shall be asserted by
the PHY when an error is detected during frame
reception. Connect to Ethernet PHY Rx_ER.
by the PHY when an error is detected during frame
reception. Connect to Ethernet PHY Rx_ER.
S3MII0_RXSYNC: Rx Sync
MII_RX_ER: Receive Error. ER shall be asserted by
the PHY when an error is detected during frame
reception. Connect to Ethernet PHY Rx_ER.
143
10
L1
RMII_RXD0
S3MII0_RXD
MII_RXD0
I
I/Ot4
RMII_RXD0/ S3MII0_RXD/ MII_RXD0: Receive
Data. RXD [3:0] transition synchronously with
respect to the RX_CLK. RXD [3:0] are driven by the
PHY. For each RX_CLK period in which DV is
asserted, RXD [3:0] transfer four bits of recovered
data from the PHY to the M825xx(2). For detailed
information, refer to IEEE 802.3 section 22.
NOTE: pin L1 does NOT have an internal pull-down
resistor.
Data. RXD [3:0] transition synchronously with
respect to the RX_CLK. RXD [3:0] are driven by the
PHY. For each RX_CLK period in which DV is
asserted, RXD [3:0] transfer four bits of recovered
data from the PHY to the M825xx(2). For detailed
information, refer to IEEE 802.3 section 22.
NOTE: pin L1 does NOT have an internal pull-down
resistor.
Total
Signals
Interface
Signals
Pin
Ethernet Interface Signal Name
Pin Compatible Mode and Enhanced Feature
Mode
Signal
Type
I/O Type
Signal Description
RMII Interface
Mode
S3MII
Interface
Mode
MII Interface
Mode
(Software
Selected)
Selected)
34
KX-TDE0110XJ / KX-TDE0110X
144
11
L2
RMII_RXD1
S3MII0PHY_M
ODE
ODE
MII_RXD1
I
Id/Ot4
RMII_RXD1: Receive Data. RXD [3:0] transition
synchronously with respect to the RX_CLK. RXD
[3:0] are driven by the PHY. For each RX_CLK
period in which DV is asserted, RXD [3:0] transfer
four bits of recovered data from the PHY to the
M825xx(2). For detailed information, refer to IEEE
802.3 section 22.
S3MII0PHY_MODE: PHY Mode
0 (Low) = Single PHY Mode (default, internal pull-
down)
1 (High) = Multi PHY Mode
Multi PHY (or Switch) Mode allows synchronizing
S3MII_TX_CLK to S3MII_RX_CLK, by connecting
S3MII_RX_CLK to S3MII_REFCLK. This allows
many S3MII buses to use the same S3MII_TX_CLK
and S3MII_TXSYNC inputs on the Multi Port PHY or
Ethernet Switch device.
MII_RXD1: Receive Data. RXD [3:0] transition syn-
chronously with respect to the RX_CLK. RXD [3:0]
are driven by the PHY. For each RX_CLK period in
which DV is asserted, RXD [3:0] transfer four bits of
recovered data from the PHY to the M825xx(2). For
detailed information, refer to IEEE 802.3 section 22.
synchronously with respect to the RX_CLK. RXD
[3:0] are driven by the PHY. For each RX_CLK
period in which DV is asserted, RXD [3:0] transfer
four bits of recovered data from the PHY to the
M825xx(2). For detailed information, refer to IEEE
802.3 section 22.
S3MII0PHY_MODE: PHY Mode
0 (Low) = Single PHY Mode (default, internal pull-
down)
1 (High) = Multi PHY Mode
Multi PHY (or Switch) Mode allows synchronizing
S3MII_TX_CLK to S3MII_RX_CLK, by connecting
S3MII_RX_CLK to S3MII_REFCLK. This allows
many S3MII buses to use the same S3MII_TX_CLK
and S3MII_TXSYNC inputs on the Multi Port PHY or
Ethernet Switch device.
MII_RXD1: Receive Data. RXD [3:0] transition syn-
chronously with respect to the RX_CLK. RXD [3:0]
are driven by the PHY. For each RX_CLK period in
which DV is asserted, RXD [3:0] transfer four bits of
recovered data from the PHY to the M825xx(2). For
detailed information, refer to IEEE 802.3 section 22.
145
12
J4
RMII_TX_EN
S3MII0_TX_C
LK
LK
MII_TX_EN
O
I/Ot16
RMII_TX_EN: Transmit Data Enable. TX_EN indi-
cates that the MAC is valid. For detailed information,
refer to IEEE 802.3 section 22.
S3MII0_TX_CLK: Tx Clock.
MII_TX_EN: Transmit Data Enable. TX_EN indi-
cates that the MAC is valid. For detailed information,
refer to IEEE 802.3 section 22.
cates that the MAC is valid. For detailed information,
refer to IEEE 802.3 section 22.
S3MII0_TX_CLK: Tx Clock.
MII_TX_EN: Transmit Data Enable. TX_EN indi-
cates that the MAC is valid. For detailed information,
refer to IEEE 802.3 section 22.
146
13
J1
RMII_TXD0
S3MII0_TXD
MII_TXD0
O
I/Ot16
RMII_TXD0/ S3MII0_TXD/ MII_TXD0: Transmit
Data. TXD [3:0] are driven by the M825xx(2), and
transition synchronously with respect to the
TX_CLK. For each TX_CLK period in which TX_EN
is asserted, TXD [3:0] are accepted for transmission
by the PHY. While TX_EN is de-asserted, TXD [3:0]
shall have no effect upon the PHY. For detailed
information, refer to IEEE 802.3 section 22.
Data. TXD [3:0] are driven by the M825xx(2), and
transition synchronously with respect to the
TX_CLK. For each TX_CLK period in which TX_EN
is asserted, TXD [3:0] are accepted for transmission
by the PHY. While TX_EN is de-asserted, TXD [3:0]
shall have no effect upon the PHY. For detailed
information, refer to IEEE 802.3 section 22.
147
14
J2
RMII_TXD1
Reserved
MII_TXD1
O
I/Ots8
RMII_TXD1/ MII_TXD1: Transmit Data. TXD [3:0]
are driven by the M825xx(2), and transition synchro-
nously with respect to the TX_CLK. For each
TX_CLK period in which TX_EN is asserted, TXD
[3:0] are accepted for transmission by the PHY.
While TX_EN is de-asserted, TXD [3:0] shall have
no effect upon the PHY. For detailed information,
refer to IEEE 802.3 section 22.
are driven by the M825xx(2), and transition synchro-
nously with respect to the TX_CLK. For each
TX_CLK period in which TX_EN is asserted, TXD
[3:0] are accepted for transmission by the PHY.
While TX_EN is de-asserted, TXD [3:0] shall have
no effect upon the PHY. For detailed information,
refer to IEEE 802.3 section 22.
148
15
R4
Reserved
Reserved
Reserved
O
I/Ot16
Reserved Output. Leave open.
149
16
H3
Reserved
S3MII0_REFC
LK
LK
MII_TX_CLK
I
Ihd/Ot4 Reserved input. Internal pull-down.
S3MII0_REFCLK: (125 MHz)
MII_TX_CLK
MII_TX_CLK
150
17
G2
Reserved
S3MII0_TXSY
NC
NC
MII_TX_ER
I/O
I/Ot16
Reserved input. Shared 100 : pull-down to GND.
S3MII0_TXSYNC
MII_TX_ER
S3MII0_TXSYNC
MII_TX_ER
151
18
F3
Reserved
Reserved
Reserved
I
Iu/Ots8 Reserved input. Internal pull-up. Leave open.
152
19
G3
Reserved
Reserved
Reserved
I
Id/Ot8
Reserved input. Internal pull-down. Leave open.
153
20
F1
Reserved
Reserved
Reserved
O
I/Ot16
Reserved Output Leave Open.
154
21
F4
Reserved
Reserved
Reserved
I
Id/Ot8
Reserved input. Internal pull-down. Leave open.
155
22
F2
Reserved
Reserved
Reserved
I
Id/Ot8
Reserved input. Internal pull-down. Leave open.
156
23
E1
Reserved
Reserved
Reserved
O
I/Ot16
Reserved Output Leave Open.
157
24
G1
Reserved
Reserved
MII_TXD2
O
Id/Ot8
Reserved Output Leave open. Internal pull-down.
MII_TXD2
MII_TXD2
158
25
G4
Reserved
Reserved
MII_TXD3
O
Id/Ot8
Reserved Output Leave open. Internal pull-down.
MII_TXD3
MII_TXD3
Total
Signals
Interface
Signals
Pin
Ethernet Interface Signal Name
Pin Compatible Mode and Enhanced Feature
Mode
Signal
Type
I/O Type
Signal Description
RMII Interface
Mode
S3MII
Interface
Mode
MII Interface
Mode
(Software
Selected)
Selected)
35
KX-TDE0110XJ / KX-TDE0110X
Note:
pin J4 has 16mA current drive, and no slew rate control.
pin J1 has 16mA current drive, and no slew rate control.
pin J1 has 16mA current drive, and no slew rate control.
Total
Signals
Interface
Signals
Pin
Utopia & 2nd SDRAM Interface Signal
Name
Signal
Type
I/O Type
Signal Description
Pin
Compatible
Mode with
Utopia Bus
Enhanced
Feature Mode
with Second
SDRAM
Interface
Enhanced
Feature
Mode with
Extra GPIO
159
1
A21
PU_MSTMO
DE#
DE#
Reserved
Reserved
I
Iu/Ot4
PU_MSTMODE#: Master# or Slave Mode Select.
Logic Low selects Master Mode.
Logic High select Slave Mode.
Reserved. Internal pull-up. Leave open.
Logic Low selects Master Mode.
Logic High select Slave Mode.
Reserved. Internal pull-up. Leave open.
160
2
D11
PUO_CLK
Reserved
Reserved
I
Ih/Ot16 PUO_CLK: Master Mode Data transfer / synchronization
clock (TLI_CLK). Clock is used to synchronize data
transfers on the bus, and the rate can be 25 MHz, 33
MHz, or 50 MHz.
Slave Mode Data transfer / synchronization clock
(RPI_CLK). Clock is used to synchronize data transfers
on the bus, and the rate can be 25 MHz, 33 MHz, or 50
MHz.
Reserved. Connect to shared to 100: pull-down to GND.
transfers on the bus, and the rate can be 25 MHz, 33
MHz, or 50 MHz.
Slave Mode Data transfer / synchronization clock
(RPI_CLK). Clock is used to synchronize data transfers
on the bus, and the rate can be 25 MHz, 33 MHz, or 50
MHz.
Reserved. Connect to shared to 100: pull-down to GND.
161
3
D4
PUO_ADR0 SDR_A09
Reserved
O
I/
Opsts66
Opsts66
PUO_ADR0: Master Mode Address (TLO_ADR[4:0]).
Address bus used to select a device (or port) on the bus.
Note that address 0x1F is the null-PHY address and
shall not be assigned to any port on the bus.
Slave Mode Address (RPI_ADR[4:0]). Address bus
used to select a device (or port) on the bus. Note that
address 0x1F is the null-PHY address and shall not be
assigned to any port on the bus.
SDR_A09: Same as SDR_A00.
Reserved. Leave open.
Address bus used to select a device (or port) on the bus.
Note that address 0x1F is the null-PHY address and
shall not be assigned to any port on the bus.
Slave Mode Address (RPI_ADR[4:0]). Address bus
used to select a device (or port) on the bus. Note that
address 0x1F is the null-PHY address and shall not be
assigned to any port on the bus.
SDR_A09: Same as SDR_A00.
Reserved. Leave open.
162
4
A3
PUO_ADR1 SDR_A10
Reserved
O
I/
Opsts66
Opsts66
PUO_ADR1: Same as PUO_ADR0.
SDR_A10: Same as SDR_A00.
Reserved. Leave open.
SDR_A10: Same as SDR_A00.
Reserved. Leave open.
163
5
B5
PUO_ADR2 SDR_A11
Reserved
O
I/
Opsts66
Opsts66
PUO_ADR2: Same as PUO_ADR0.
SDR_A11: Same as SDR_A00.
Reserved. Leave open.
SDR_A11: Same as SDR_A00.
Reserved. Leave open.
164
6
C5
PUO_ADR3 SDR_A12
Reserved
O
I/
Opsts66
Opsts66
PUO_ADR3: Same as PUO_ADR0.
SDR_A12: Same as SDR_A00.
Reserved. Leave open.
SDR_A12: Same as SDR_A00.
Reserved. Leave open.
165
7
D5
PUO_ADR4 SDR_A13
Reserved
O
I/
Opsts66
Opsts66
PUO_ADR4: Same as PUO_ADR0.
SDR_A13: Same as SDR_A00.
Reserved. Leave open.
SDR_A13: Same as SDR_A00.
Reserved. Leave open.
166
8
A5
PUO_DAT00 SDR_A14
(BS0)
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT00: Master Mode Data signal (OB_DAT).
Packet Data Bus carries the packet octets. Data must be
in big-endian order. Bits are in the following order: 15, 14
... 8, 7, 6 ... 1, 0.
Slave Mode Data signal (OB_DAT). Packet Data Bus
carries the packet octets. Data must be in big endian
order. Bits are in the following order: 15, 14 ... 8, 7, 6 ...
1, 0.
SDR_A14(BS0): SDRAM Bank Select. For example:
Connect SDR_A14/BA0 to SDRAM BA0.
Connect SDR_A15/BA1 to SDRAM BA1.
Reserved. Leave open.
Packet Data Bus carries the packet octets. Data must be
in big-endian order. Bits are in the following order: 15, 14
... 8, 7, 6 ... 1, 0.
Slave Mode Data signal (OB_DAT). Packet Data Bus
carries the packet octets. Data must be in big endian
order. Bits are in the following order: 15, 14 ... 8, 7, 6 ...
1, 0.
SDR_A14(BS0): SDRAM Bank Select. For example:
Connect SDR_A14/BA0 to SDRAM BA0.
Connect SDR_A15/BA1 to SDRAM BA1.
Reserved. Leave open.
167
9
B6
PUO_DAT01 SDR_A15
(BS1)
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT01: Same as PUO_DAT00.
SDR_A15 (BS1): Same as SDR_A14 (BS0).
Reserved. Leave open.
SDR_A15 (BS1): Same as SDR_A14 (BS0).
Reserved. Leave open.
168
10
C6
PUO_DAT02 SDR_CS1#
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT02: Same as PUO_DAT00.
SDR_CS1#: SDRAM Chip Select 1. Active low SDRAM
Chip Select 1. Leave open if not used.
NOTE: SDRAM device chip select pins must be con-
nected to SDR_CS1_N, i.e., they must not be connected
to ground.
Reserved. Leave open.
SDR_CS1#: SDRAM Chip Select 1. Active low SDRAM
Chip Select 1. Leave open if not used.
NOTE: SDRAM device chip select pins must be con-
nected to SDR_CS1_N, i.e., they must not be connected
to ground.
Reserved. Leave open.
36
KX-TDE0110XJ / KX-TDE0110X
169
11
D6
PUO_DAT03 SDR_WE#
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT03: Same as PUO_DAT00.
SDR_WE#: Write Enable. WR# is an active low output
used to enable data transfer from the SDR_DATA[31:00]
lines to the selected device. Connect to SDRAM WE#
pin.
Reserved. Leave open.
SDR_WE#: Write Enable. WR# is an active low output
used to enable data transfer from the SDR_DATA[31:00]
lines to the selected device. Connect to SDRAM WE#
pin.
Reserved. Leave open.
170
12
A6
PUO_DAT04 SDR_RAS#
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT04: Same as PUO_DAT00.
SDR_RAS#: Row Address Strobe. RAS# is an active
low output used by the SDRAM to define the SDRAM
operation commands in conjunction with the CAS# and
WR# signals and is latched by the SDRAM at the posi-
tive edge of CLK. Connect to SD RAM RAS# pin.
Reserved. Leave open.
SDR_RAS#: Row Address Strobe. RAS# is an active
low output used by the SDRAM to define the SDRAM
operation commands in conjunction with the CAS# and
WR# signals and is latched by the SDRAM at the posi-
tive edge of CLK. Connect to SD RAM RAS# pin.
Reserved. Leave open.
171
13
B7
PUO_DAT05 SDR_CAS#
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT05: Same as PUO_DAT00.
SDR_CAS#: Column Address Strobe. CAS# is an active
low output used by the SDRAM to define the SDRAM
operation commands in conjunction with the RAS# and
WR# signals and is latched at the positive edge of CLK.
Connect to SDRAM CAS# pin.
Reserved. Leave open.
SDR_CAS#: Column Address Strobe. CAS# is an active
low output used by the SDRAM to define the SDRAM
operation commands in conjunction with the RAS# and
WR# signals and is latched at the positive edge of CLK.
Connect to SDRAM CAS# pin.
Reserved. Leave open.
172
14
C7
PUO_DAT06 SDR_DQM0
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT06: Same as PUO_DAT00.
SDR_DQM0: SDRAM Data Mask [0]. Connect
SDR_DQM[3:0] to SDRAM DQM[3:0], respectively.
Reserved. Leave open.
SDR_DQM0: SDRAM Data Mask [0]. Connect
SDR_DQM[3:0] to SDRAM DQM[3:0], respectively.
Reserved. Leave open.
173
15
D7
PUO_DAT07 SDR_DQM1
Reserved
O
I/
Opsts66
Opsts66
PUO_DAT07: Same as PUO_DAT00.
SDR_DQM1: Same as SDR_DQM0.
Reserved. Leave open.
SDR_DQM1: Same as SDR_DQM0.
Reserved. Leave open.
174
16
A7
PUO_DAT08 SDR_DATA00 Reserved
I/O
I/
Opsts66
Opsts66
PUO_DAT08: Same as PUO_DAT00.
SDR_DATA00: Second SDRAM Bus Data [00].
Connect to SDRAM device Data pin.
Reserved. Leave open.
SDR_DATA00: Second SDRAM Bus Data [00].
Connect to SDRAM device Data pin.
Reserved. Leave open.
175
17
B8
PUO_DAT09 SDR_DATA08 Reserved
I/O
I/
Opsts66
Opsts66
PUO_DAT09: Same as PUO_DAT00.
SDR_DATA08: Same as SDR_DATA00.
Reserved. Leave open.
SDR_DATA08: Same as SDR_DATA00.
Reserved. Leave open.
176
18
C8
PUO_DAT10 SDR_DATA01 Reserved
I/O
I/
Opsts66
Opsts66
PUO_DAT10: Same as PUO_DAT00.
SDR_DATA01: Same as SDR_DATA00.
Reserved. Leave open.
SDR_DATA01: Same as SDR_DATA00.
Reserved. Leave open.
177
19
D8
PUO_DAT11 SDR_DATA09 Reserved
I/O
I/
Opsts66
Opsts66
PUO_DAT11: Same as PUO_DAT00.
SDR_DATA09: Same as SDR_DATA00.
Reserved. Leave open.
SDR_DATA09: Same as SDR_DATA00.
Reserved. Leave open.
178
20
A8
PUO_DAT12 SDR_DATA02 Reserved
I/O
I/
Opsts66
Opsts66
PUO_DAT12: Same as PUO_DAT00.
SDR_DATA02: Same as SDR_DATA00.
Reserved. Leave open.
SDR_DATA02: Same as SDR_DATA00.
Reserved. Leave open.
179
21
B9
PUO_DAT13 SDR_DATA10 Reserved
I/O
I/
Opsts66
Opsts66
PUO_DAT13: Same as PUO_DAT00.
SDR_DATA10: Same as SDR_DATA00.
Reserved. Leave open.
SDR_DATA10: Same as SDR_DATA00.
Reserved. Leave open.
180
22
C9
PUO_DAT14 SDR_DATA03 PCI_REQ3#
I/O
I/
Opsts66
Opsts66
PUO_DAT14: Same as PUO_DAT00.
SDR_DATA03: Same as SDR_DATA00.
PCI_REQ3#: Request. REQ# is used to indicate to the
arbiter that this agent desires use of the bus. Connect to
PCI Bus: REQ#.
SDR_DATA03: Same as SDR_DATA00.
PCI_REQ3#: Request. REQ# is used to indicate to the
arbiter that this agent desires use of the bus. Connect to
PCI Bus: REQ#.
181
23
D9
PUO_DAT15 SDR_DATA11 PCI_GNT3#
I/O
I/
Opsts66
Opsts66
PUO_DAT15: Same as PUO_DAT00.
SDR_DATA11: Same as SDR_DATA00.
PCI_GNT3#: Grant. GNT# is used to indicate to the
agent that access to the bus has been granted. Connect
to PCI Bus: GNT#.
SDR_DATA11: Same as SDR_DATA00.
PCI_GNT3#: Grant. GNT# is used to indicate to the
agent that access to the bus has been granted. Connect
to PCI Bus: GNT#.
Total
Signals
Interface
Signals
Pin
Utopia & 2nd SDRAM Interface Signal
Name
Signal
Type
I/O Type
Signal Description
Pin
Compatible
Mode with
Utopia Bus
Enhanced
Feature Mode
with Second
SDRAM
Interface
Enhanced
Feature
Mode with
Extra GPIO
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