DOWNLOAD Harman Kardon HK 990 Service Manual ↓ Size: 7.9 MB | Pages: 127 in PDF or view online for FREE

Model
HK 990
Pages
127
Size
7.9 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hk-990.pdf
Date

Harman Kardon HK 990 Service Manual ▷ View online

29AL016D
S29AL016D_00_A2 December 17, 2004
P r e l i m i n a r y
Pin Configuration
A0–A19
=
20 addresses
DQ0–DQ14
=
15 data inputs/outputs
DQ15/A-1
=
DQ15 (data input/output, word mode),  
A-1 (LSB address input, byte mode)
BYTE#
=
Selects 8-bit or 16-bit mode
CE#
=
Chip enable
OE#
= Output 
enable
WE#
=
Write enable
RESET#
=
Hardware reset pin
RY/BY#
= Ready/Busy 
output 
V
CC
 
=
3.0 volt-only single power supply 
(see Product Selector Guide for speed 
options and voltage supply tolerances)
V
SS
=
Device  ground
NC
=
Pin not connected internally
Logic Symbol
20
16 or 8
DQ0–DQ15
(A-1)
A0–A19
CE#
OE#
WE#
RESET#
BYTE#
RY/BY# 
39
S29AL016D
S29AL016D_00_A2 December 17, 2004
P r e l i m i n a r y
Physical Dimensions
TS 048—48-Pin Standard TSOP
40
December 17, 2004 S29AL016D_00_A2
S29AL016D
P r e l i m i n a r y
* For reference only. BSC is an ANSI standard for Basic Space Centering.
6
2
3
4
5
7
8
9
MO-142 (D) DD
48
MIN
0.05
0.95
0.17
0.17
0.10
0.10
18.30
19.80
0.50
0.08
11.90
0.50 BASIC
MAX
0.15
1.20
0.27
0.16
0.21
0.20
18.50
12.10
0.70
20.20
0.23
1.05
0.20
1.00
0.22
18.40
20.00
0.60
12.00
NOM
Symbol
Jedec
b1
A2
A1
A
D
L
e
E
D1
b
c1
c
0
R
N
1
NOTES:
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
TO BE DETERMINED AT THE SEATING PLANE  -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF 
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT 
HORIZONTAL SURFACE.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE 
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
N
+1
2
N
1
2
N
3
REVERSE PIN OUT (TOP VIEW)
C
e
A1
A2
2X (N/2 TIPS)
0.10
9
SEATING
PLANE
A
SEE DETAIL A
B
B
A
B
E
D1
D
2X
2X (N/2 TIPS)
0.25
2X
0.10
0.10
N
5
+1
N
2
4
5
1
N
2
2
STANDARD PIN OUT (TOP VIEW)
SEE DETAIL B
DETAIL A
(c)
θ°
L
0.25MM (0.0098") BSC
C
R
GAUGE PLANE
PARALLEL TO
SEATING PLANE
b
b1
(c)
7
6
c1
WITH PLATING
BASE METAL
7
0.08MM     (0.0031")      M    C  A - B   S
SECTION B-B
DETAIL B
X
e/2
X = A OR B
3355 \ 16-038.10c
41
www.ti.com
FEATURES
, DW
, NS, OR PW 
ACKAGE
(T
OP VIEW)
1
2
3
4
5
6
7
8
9
10
1
1
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D 
2D 
3D 
4D 
5D 
6D 
7D 
8D 
9D
CLR
GND
V
C
C
1Q 
2Q 
3Q 
4Q 
5Q 
6Q 
7Q 
8Q 
9Q 
CLKEN 
CLK
DESCRIPTION/ORDERING INFORMATION
SN74LVC823A
9-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS305I – MARCH 1993 – REVISED FEBRUARY 2005
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t
pd
of 7.9 ns at 3.3 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is
particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and
working registers.
With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high
transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. This device has
noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low,
independently of the clock.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube of 25
SN74LVC823ADW
SOIC – DW
LVC823A
Reel of 2000
SN74LVC823ADWR
SOP – NS
Reel of 2000
SN74LVC823ANSR
LVC823A
SSOP – DB
Reel of 2000
SN74LVC823ADBR
LC823A
–40
°
C to 85
°
C
Tube of 60
SN74LVC823APW
TSSOP – PW
Reel of 2000
SN74LVC823APWR
LC823A
Reel of 250
SN74LVC823APWT
TVSOP – DGV
Reel of 2000
SN74LVC823ADGVR
LC823A
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
42
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