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This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for 
use of circuits described. No patent licenses are implied.
Rev. 1.5 / Feb. 2005

1.0

First Version Release

Nov. 2004

1. Changed tOH: 2.0 --> 2.5
    [tCK = 7 & 7.5 (CL3) Product]

1.1

1. Changed Input High/Low Voltage (Page 08)
2. Changed DC characteristics (Page 09)
   - IDD2NS: 18mA -> 15mA
   - IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA
     [Speed 200 / 166 / 143 / 133MHz]
3. Changed Clock High / Low pulse width Time (Page 11)
4. Changed tAC Time (Page11)
5. Changed tRRD Time (Page12)

Dec. 2004

1.2

1. Corrected Revision No.: 2.0 -> 1.1
2. Deleted Remark at Revision History
3. Corrected AC OPERATING CONDITION 
   - CL 50pF -> 30pF
4. Changed DC OPERATING CONDITION
   - VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0
   - VIL MIN VSSQ-2.0 -> -0.3

Dec. 2004

1.3

1. Modified note for Super Low Power in ORDERING INFORMATION

Jan. 2005

1.4

1. Corrected PIN ASSIGNMENT A12 to NC

Jan. 2005

1.5

1. Corrected comments for overshoot and undershoot

Feb. 2005

31

Synchronous DRAM Memory 64Mbit (4Mx16bit)

HY57V641620E(L/S)T(P)-xI Series

The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of
1,048,576x16. 

HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)

Note: 1. HY57V641620ET-xI Series: Normal power, Leaded.
         2. HY57V641620ELT-xI Series: Low power, Leaded.
         3. HY57V641620EST-xI Series: Super Low power, Leaded.
         4. HY57V641620ETP-xI Series: Normal power, Lead Free.
         5. HY57V641620ELTP-xI Series: Low power, Lead Free.
         6. HY57V641620ESTP-xI Series: Super Low Power, Lead Free

HY57V641620E(L/S)T(P)-5I

200MHz

4Banks x 1Mbits x16

LVTTL

54 Pin TSOPII

HY57V641620E(L/S)T(P)-6I

166MHz

HY57V641620E(L/S)T(P)-7I

143MHz

HY57V641620E(L/S)T(P)-HI

133MHz

•

Voltage: VDD, VDDQ 3.3V supply voltage

•

All device pins are compatible with LVTTL interface

•  54 Pin TSOPII (Lead or Lead Free Package)

•

All inputs and outputs referenced to positive edge of 
system clock

•

Data mask function by UDQM, LDQM

•

Internal four banks operation

•

Auto refresh and self refresh

•

4096 Refresh cycles / 64ms 

•

Programmable Burst Length and Burst Type

 - 1, 2, 4, 8 or full page for Sequential Burst

 - 1, 2, 4 or 8 for Interleave Burst

•

Programmable CAS Latency; 2, 3 Clocks

•

Burst Read Single Write operation

32

Synchronous DRAM Memory 64Mbit (4Mx16bit)

HY57V641620E(L/S)T(P)-xI Series

VDD
DQ0

VDDQ

DQ1
DQ2

VSSQ

DQ3
DQ4

VDDQ

DQ5
DQ6

VSSQ

DQ7
VDD

LDQM

/WE

/CAS
/RAS

/CS

BA0
BA1

A10/AP

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

54 Pin TSOPII

400mil x 875mil

0.8mm pin pitch

33

Synchronous DRAM Memory 64Mbit (4Mx16bit)

HY57V641620E(L/S)T(P)-xI Series

CLK

Clock

The system clock input. All other inputs are registered to the 
SDRAM on the rising edge of CLK

CKE

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will 
be one of the states among power down, suspend or self refresh

CS

Chip Select

Enables or disables all inputs except CLK, CKE, UDQM and LDQM

BA0, BA1

Bank Address

Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity

A0 ~ A11

Address

Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10

RAS, CAS, WE

Row Address Strobe,

Column Address Strobe, 

Write Enable

RAS, CAS and WE define the operation
Refer function truth table for details

UDQM, LDQM

Data Input/Output Mask

Controls output buffers in read mode and masks input data in write 
mode

DQ0 ~ DQ15

Data Input / Output

Multiplexed data input / output pin

VDD / VSS

Power Supply / Ground

Power supply for internal circuits and input buffers

VDDQ / VSSQ

Data Output Power / 

Ground

Power supply for output buffers

NC

No Connection

No connection

34