Harman Kardon HK 990 Service Manual ▷ View online
83905AM
http://www.icst.com/products/hiperclocks.html
REV. A JANUARY 20, 2005
Integrated
Circuit
Systems, Inc.
Circuit
Systems, Inc.
ICS83905
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83905 is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83905 single ended
clock input accepts LVCMOS or LVTTL input lev-
LVTTL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83905 single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50
to drive 50
Ω series or parallel terminated transmission lines.
The effective fanout can be increased from 6 to 12 by utilizing
the ability of the outputs to drive two series terminated lines.
the ability of the outputs to drive two series terminated lines.
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew char-
acteristics along with the 1.8V output capabilities makes the
ICS83905 ideal for high performance, single ended applica-
tions that also require a limited output voltage.
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew char-
acteristics along with the 1.8V output capabilities makes the
ICS83905 ideal for high performance, single ended applica-
tions that also require a limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
• 6 LVCMOS / LVTTL outputs
• Crystal oscillator interface
• Output frequency range: 10MHz to 50MHz
• Crystal input frequency range: 10MHz to 50MHz
• Output skew: 10ps (typical)
• 5V tolerant enable inputs
• Synchronous output enables
• Operating supply modes: Full 3.3V, 2.5V and 1.8V,
• Crystal oscillator interface
• Output frequency range: 10MHz to 50MHz
• Crystal input frequency range: 10MHz to 50MHz
• Output skew: 10ps (typical)
• 5V tolerant enable inputs
• Synchronous output enables
• Operating supply modes: Full 3.3V, 2.5V and 1.8V,
mixed 3.3Vcore/2.5V or1.8V operating supply, and
mixed 2.5V core/1.8V operating supply
mixed 2.5V core/1.8V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
• Pin compatible to MPC905
• Industrial version available upon request
• Lead-Free package fully RoHS compliant
• Pin compatible to MPC905
• Industrial version available upon request
HiPerClockS™
ICS
ICS83905
16-Lead SOIC
3.9mm x 9.9mm x 1.38mm body package
M Pacakge
Top View
ICS83905
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm body package
G Pacakge
Top View
SYNCHRONIZE
SYNCHRONIZE
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
ENABLE 1
ENABLE 2
XTAL_IN
XTAL_OUT
XTAL_OUT
ENABLE 2
GND
BCLK0
V
DD
o
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
16
15
14
13
12
11
10
15
14
13
12
11
10
9
XTAL_IN
ENABLE 1
BCLK5
V
ENABLE 1
BCLK5
V
DDO
BCLK4
GND
BCLK3
V
GND
BCLK3
V
DD
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
20 19 18 17 16
6 7 8 9 10
1
2
3
4
5
15
14
13
12
11
ENABLE2
XT
AL_OUT
XT
AL_IN
ENABLE1
nc
BCLK5
V
DDO
BCLK4
GND
GND
GND
GND
BCLK0
V
DDO
BCLK1
GND
GND
BCLK2
V
DD
BCLK3
ICS83905
20-Lead VFQFN
4mm x 4mm x 0.9mm
body package
K Package
Top View
11
FEATURES
●
SUPERIOR SOUND QUALITY
●
ULTRA LOW DISTORTION: 0.00008%
●
LOW NOISE: 8nV/
√
Hz
●
TRUE FET-INPUT: I
B
= 5pA
●
HIGH SPEED:
SLEW RATE: 20V/
µ
s
BANDWIDTH: 8MHz
●
HIGH OPEN-LOOP GAIN: 120dB (600
Ω
)
●
WIDE SUPPLY RANGE:
±
2.5V to
±
18V
●
SINGLE, DUAL, AND QUAD VERSIONS
High Performance
AUDIO OPERATIONAL AMPLIFIERS
TM
DESCRIPTION
The OPA134 series are ultra-low distortion, low noise
operational amplifiers fully specified for audio appli-
cations. A true FET input stage was incorporated to
provide superior sound quality and speed for excep-
tional audio performance. This in combination with
high output drive capability and excellent dc perfor-
mance allows use in a wide variety of demanding
applications. In addition, the OPA134’s wide output
swing, to within 1V of the rails, allows increased
headroom making it ideal for use in any audio circuit.
operational amplifiers fully specified for audio appli-
cations. A true FET input stage was incorporated to
provide superior sound quality and speed for excep-
tional audio performance. This in combination with
high output drive capability and excellent dc perfor-
mance allows use in a wide variety of demanding
applications. In addition, the OPA134’s wide output
swing, to within 1V of the rails, allows increased
headroom making it ideal for use in any audio circuit.
OPA134 op amps are easy to use and free from phase
inversion and overload problems often found in com-
mon FET-input op amps. They can be operated from
inversion and overload problems often found in com-
mon FET-input op amps. They can be operated from
±2.5V to ±18V power supplies. Input cascode cir-
cuitry provides excellent common-mode rejection and
maintains low input bias current over its wide input
voltage range, minimizing distortion. OPA134 series
op amps are unity-gain stable and provide excellent
dynamic behavior over a wide range of load condi-
tions, including high load capacitance. The dual and
quad versions feature completely independent cir-
cuitry for lowest crosstalk and freedom from interac-
tion, even when overdriven or overloaded.
cuitry provides excellent common-mode rejection and
maintains low input bias current over its wide input
voltage range, minimizing distortion. OPA134 series
op amps are unity-gain stable and provide excellent
dynamic behavior over a wide range of load condi-
tions, including high load capacitance. The dual and
quad versions feature completely independent cir-
cuitry for lowest crosstalk and freedom from interac-
tion, even when overdriven or overloaded.
Single and dual versions are available in 8-pin DIP
and SO-8 surface-mount packages in standard con-
figurations. The quad is available in 14-pin DIP and
SO-14 surface mount packages. All are specified for
–40
and SO-8 surface-mount packages in standard con-
figurations. The quad is available in 14-pin DIP and
SO-14 surface mount packages. All are specified for
–40
°C to +85°C operation. A SPICE macromodel is
available for design analysis.
APPLICATIONS
●
PROFESSIONAL AUDIO AND MUSIC
●
LINE DRIVERS
●
LINE RECEIVERS
●
MULTIMEDIA AUDIO
●
ACTIVE FILTERS
●
PREAMPLIFIERS
●
INTEGRATORS
●
CROSSOVER NETWORKS
© 1996 Burr-Brown Corporation
PDS-1339C
Printed in U.S.A. December, 1997
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
1
2
3
4
8
7
6
5
V+
Out B
–In B
+In B
Out A
–In A
+In A
V–
OPA2134
8-Pin DIP, SO-8
A
B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Out D
–In D
+In D
V–
+In C
–In C
Out C
Out A
–In A
+In A
V+
+In B
–In B
Out B
OPA4134
14-Pin DIP
SO-14
A
D
B
C
1
2
3
4
8
7
6
5
Offset Trim
V+
Output
NC
Offset Trim
–In
+In
V–
OPA134
8-Pin DIP, SO-8
®
OPA134
OPA2134
OPA4134
OPA4134
OPA134
OPA2134
OPA4134
OPA4134
OPA134
OPA2134
12
www.ti.com
FEATURES
DB, DBQ, DGV, DW,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
P0
P1
P2
P3
A1
A2
P0
P1
P2
P3
GND
V
CC
SDA
SCL
INT
P7
P6
P5
P4
SCL
INT
P7
P6
P5
P4
RGV PACKAGE
(TOP VIEW)
16
6
8
2
10
P7
P5
V
CC
4
3
1
7
5
12
11
9
13
14
15
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
RGT PACKAGE
(TOP VIEW)
16
6
8
2
10
P7
P5
V
CC
4
3
1
7
5
12
11
9
13
14
15
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
P1
P2
DESCRIPTION/ORDERING INFORMATION
PCA9554A
REMOTE 8-BIT I
2
C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS127A – SEPTEMBER 2006 – REVISED FEBRUARY 2007
•
I
2
C to Parallel Port Expander
•
Power-Up With All Channels Configured as
Inputs
Inputs
•
Open-Drain Active-Low Interrupt Output
•
No Glitch on Power-Up
•
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
2.3 V to 5.5 V
•
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Maximum Capability for Directly Driving LEDs
•
5-V Tolerant I/Os
•
Latch-Up Performance Exceeds 100 mA Per
•
400-kHz Fast I
2
C Bus
JESD 78, Class II
•
Three Hardware Address Pins Allow up to
•
ESD Protection Exceeds JESD 22
Eight Devices on the I
2
C/SMBus
–
2000-V Human-Body Model (A114-A)
•
Input/Output Configuration Register
–
200-V Machine Model (A115-A)
•
Polarity Inversion Register
–
1000-V Charged-Device Model (C101)
•
Internal Power-On Reset
This 8-bit I/O expander for the two-line bidirectional bus (I
2
C) is designed for 2.3-V to 5.5-V V
CC
operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I
2
C interface [serial
clock (SCL), serial data (SDA)].
The PCA9554A consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high or active low) registers. At power-on, the I/Os are configured as inputs with a weak pull up
to V
Inversion (active high or active low) registers. At power-on, the I/Os are configured as inputs with a weak pull up
to V
CC
. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The
polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by
the system master.
polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by
the system master.
The system master can reset the PCA9554A in the event of a timeout or other improper operation by utilizing
the power-on reset feature which puts the registers in their default state and initializes the I
the power-on reset feature which puts the registers in their default state and initializes the I
2
C/SMBus state
machine.
The PCA9554A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I
2
C bus. Thus, the PCA9554A can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current
consumption.
consumption.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS
OTHERWISE
NOTED
this
document
contains
Copyright © 2006–2007, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
13
SRC4392
FEATURES
SRC4392
SBFS029B – DECEMBER 2005 – REVISED APRIL 2006
Two-Channel, Asynchronous Sample Rate Converter with
Integrated Digital Audio Interface Receiver and Transmitter
•
Digital Audio Interface Receiver (DIR)
•
Two-Channel Asynchronous Sample Rate
– PLL Lock Range Includes Sampling Rates
Converter (SRC)
from 20kHz to 216kHz
– Dynamic Range with –60dB Input
– Includes Four Differential Input Line
(A-Weighted): 144dB typical
Receivers and an Input Multiplexer
– Total Harmonic Distortion and Noise
– Bypass Multiplexer Routes Line Receiver
(THD+N) with Full-Scale Input: –140dB
Outputs to Line Driver and Buffer Outputs
typical
– Block-Sized Data Buffers for Both Channel
– Supports Audio Input and Output Data
Status and User Data
Word Lengths Up to 24 Bits
– Automatic Detection of Non-PCM Audio
– Supports Input and Output Sampling
Streams (DTS CD/LD and IEC 61937
Frequencies Up to 216kHz
formats)
– Automatic Detection of the Input-to-Output
– Audio CD Q-Channel Sub-Code Decoding
Sampling Ratio
and Data Buffer
– Wide Input-to-Output Conversion Range:
– Status Registers and Interrupt Generation
16:1 to 1:16 Continuous
for Flag and Error Conditions
– Excellent Jitter Attenuation Characteristics
– Low Jitter Recovered Clock Output
– Digital De-Emphasis Filtering for 32kHz,
•
Two Audio Serial Ports (Ports A and B)
44.1kHz, and 48kHz Input Sampling Rates
– Synchronous Serial Interface to External
– Digital Output Attenuation and Mute
Signal Processors, Data Converters, and
Functions
Logic
– Output Word Length Reduction
– Slave or Master Mode Operation with
Sampling Rates up to 216kHz
– Status Registers and Interrupt Generation
for Sampling Ratio and Ready Flags
– Supports Left-Justified, Right-Justified, and
Philips I
2
S™ Data Formats
•
Digital Audio Interface Transmitter (DIT)
– Supports Audio Data Word Lengths Up to
– Supports Sampling Rates Up to 216kHz
24 Bits
– Includes Differential Line Driver and
•
Four General-Purpose Digital Outputs
CMOS Buffered Outputs
– Multifunction Programmable Via Control
– Block-Sized Data Buffers for Both Channel
Registers
Status and User Data
•
Extensive Power-Down Support
– Status Registers and Interrupt Generation
for Flag and Error Conditions
– Functional Blocks May Be Disabled
Individually When Not In Use
•
User-Selectable Serial Host Interface: SPI or
Philips I
Philips I
2
C™
•
Operates From +1.8V Core and +3.3V I/O
Power Supplies
Power Supplies
– Provides Access to On-Chip Registers and
Data Buffers
•
Small TQFP-48 Package, Compatible with the
SRC4382 and DIX4192
SRC4382 and DIX4192
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Dolby is a registered trademark of Dolby Laboratories.
I2C, I2S are trademarks of Koninklijke Philips Electronics N.V.
All other trademarks are the property of their respective owners.
I2C, I2S are trademarks of Koninklijke Philips Electronics N.V.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
14
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