Harman Kardon HK 990 Service Manual ▷ View online
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
T
o Eight Other Channels
1D
1Q
C
CLK
OE
CLR
1
1
1
14
13
2
R
1D
C1
23
SN74LVC823A
9-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
9-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS305I – MARCH 1993 – REVISED FEBRUARY 2005
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. OE does not affect the internal operations of the latch. Previously
stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
low logic levels) or the high-impedance state. OE does not affect the internal operations of the latch. Previously
stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OUTPUT
Q
OE
CLR
CLKEN
CLK
D
L
L
X
X
X
L
L
H
L
↑
H
H
L
H
L
↑
L
L
L
H
H
X
X
Q
0
H
X
X
X
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
43
041002
FEATURES
§ Automatically restarts a microprocessor after
power failure
§ Monitors pushbutton for external override
§ Maintains reset for 150 ms after V
CC
returns
to an in-tolerance condition
§ Reduces need for discrete components
§ Precision temperature-compensated voltage
reference and voltage sensor
§ Accurate 5%, 10% or 20% power monitoring
§ Low-cost TO-92 or space saving surface
mount SOT-23 packages available
§ Efficient open-drain output with internal
5.5 k
W pull-up resistor
§ Operating temperature -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTION
TO-92
1
RST
Active Low Reset Output
2 V
CC
Power
Supply
3 GND
Ground
SOT-23
1
RST
Active Low Reset Output
2 V
CC
Power
Supply
3 GND
Ground
DESCRIPTION
The DS1818 EconoReset uses a precision temperature-compensated reference and comparator circuit to
monitor the status of the power supply (V
monitor the status of the power supply (V
CC
). When an out-of-tolerance condition is detected, an internal
power-fail signal is generated which forces reset to the active state. When V
CC
returns to an in-tolerance
condition, the reset signal is kept in the active state for approximately 150 ms to allow the power supply
and processor to stabilize.
and processor to stabilize.
The DS1818 also monitors a pushbutton on the reset output. If the reset line is pulled low, a reset is
generated upon release and the DS1818 output will be held in reset output low for typically 150 ms.
generated upon release and the DS1818 output will be held in reset output low for typically 150 ms.
DS1818
3.3V EconoReset with Pushbutton
www.maxim-ic.com
1
2
3
TOP VIEW
SOT-23 PACKAGE
See Mech.
Drawings Section
On Website
1 2 3
1 2 3
BOTTOM VIEW
TO-92 PACKAGE
See Mech.
Drawings Section
On Website
DALLAS
DS1818
Econo
Reset
44
© 2005 Fairchild Semiconductor Corporation
DS500218
www.fairchildsemi.com
March 1999
Revised February 2005
NC7WZ07 T
inyLogi
c
£
UHS
Dual
B
u
u
ff
er (Open D
rai
n
Outp
ut
s)
NC7WZ07
TinyLogic
TinyLogic
£
UHS Dual Buffer (Open Drain Outputs)
General Description
The NC7WZ07 is a dual buffer with open drain outputs
from Fairchild's Ultra High Speed Series of TinyLogic
from Fairchild's Ultra High Speed Series of TinyLogic
£
in
the space saving SC70 6-lead package. The device is fab-
ricated with advanced CMOS technology to achieve ultra
high speed with high output drive while maintaining low
static power dissipation over a very broad V
ricated with advanced CMOS technology to achieve ultra
high speed with high output drive while maintaining low
static power dissipation over a very broad V
CC
operating
range. The device is specified to operate over the 1.65V to
5.5V V
5.5V V
CC
range. The inputs and outputs are high imped-
ance when V
CC
is 0V. Inputs tolerate voltages up to 7V
independent of V
CC
operating voltage.
Features
■
Space saving SC70 6-lead package
■
Ultra small MicroPak
¥
Pb-Free leadless package
■
Ultra High Speed: t
PZL
2.3 ns Typ into 50 pF at 5V V
CC
■
High I
OL
Output Drive:
24 mA at 3V V
CC
■
Broad V
CC
Operating Range: 1.65V to 5.5V
■
Matches the performance of LCX when operated at
3.3V V
3.3V V
CC
■
Power down high impedance inputs/outputs
■
Overvoltage tolerant inputs facilitate 5V to 3V translation
■
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
TinyLogic
£
is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak
¥
is a trademark of Fairchild Semiconductor Corporation.
Order
Package Product
Code
Package Description
Supplied As
Number
Number
Top Mark
NC7WZ07P6X
MAA06A
Z07
6-Lead SC70, EIAJ SC88, 1.25mm Wide
3k Units on Tape and Reel
NC7WZ07P6X_NL
(Note 1)
(Note 1)
MAA06A
Z07
Pb-Free 6-Lead SC70, EIAJ SC88, 1.25mm
Wide
Wide
3k Units on Tape and Reel
NC7WZ07L6X
MAC06A
D3
Pb-Free 6-Lead MicroPak, 1.0mm Wide
5k Units on Tape and Reel
45
www.fairchildsemi.com
NC7W
Z07
Logic Symbol
IEEE/IEC
Pin Descriptions
Function Table
Y
A
H
HIGH Logic Level
L
LOW Logic Level
Connection Diagrams
Pin Assignments for SC70
(Top View)
Pin One Orientation Diagram
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Thru View)
Pin Names
Description
A
1
, A
2
Data Inputs
Y
1
, Y
2
Output
Input
Output
A
Y
L
L
H
Z
46
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