Sony DVP-S7000 (serv.man2) Service Manual ▷ View online
– 54 –
3-1-1. Attenuation of OP Output Signals
The RF signals (RFP, RFM) output from OP for DVD are attenuated by R075 and R039 so
that they satisfy the input amplitude allowable level of IC001 in the post stage.
(About 1V
PPD
(*3) for SL (*1) disc. In actual, RFM signal is an RFP signal because it is
connected to GND in OP block.)
3-1-2. HPF
Low frequency component of the attenuated RF signal is removed by a high pass filter
(HPF) that cuts off the frequency (about 3.16kHz) determined by the input impedance of
C043, C044, and IC001, then it is entered to the IC001.
3-1-3. RF Front End Processing: IC001 SSI33P3720
(1) ATT block
The RF signal entered from IC001 RFP^£ and RFM^¢ is entered to the ATT block.
In this block, this processing is executed to attenuate the signal below signal amplitude
level determined according to the specification (about 200mV
PPD
, determined
depending on AGC input allowable level) in order to utilize high performance of IC.
After processing, the signal is output from IC001 ATOP^™ and ATON^¡.
ATT: Set to 3/16 for SL disc, or 5/16 for DL (*2) disc.
These are operated by the command register set via serial interface.
(2) AGC block
ATT output IC001 ATOP^™ and ATON^¡ are processed below AGC allowable level
as mentioned above, then they are AC-coupled by C045 and C046, and entered
respectively to AGC block input IC001 AIP%ª and AIN^º.
The AGC block controls gain of AGC amplifier so that constant input signal (1V
PPD
)
is supplied to the IC001 DIP%£ and DIN%¢. The AGC compares full-wave rectified
input signal to IC001 DIP%£ and DIN%¢ with reference level, and repeats slow decay
and slow attack while keeping a balance with the product of current by time so as to
attain the optimum gain.
Slow decay: When input signal to IC001 DIP%£ and DIN%¢ is below 1V
PPD
, C047
(C
BYP
) is charged with 4µA slow decay current. In this case, AGC
amplifier gain gradually increases.
Slow attack: When input signal to IC001 DIP%£ and DIN%¢ is over 1V
PPD
, C047
(C
BYP
) is discharged with 0.18mA slow attack current. In this case, AGC
amplifier gain gradually decreases.
– 55 –
The input signal to IC001 DIP%£ and DIN%¢ is a signal processed after EQ block
mentioned later.
*1: Single Layer disc
*2: Dual Layer disc
*3: Peak to Peak Differential
(3) EQ block
The EQ block is a programmable equalizer filter differentiator block.
The DVD format is premised on the EQ and requires high frequency signals to be
boosted. This block equalizes RF signal to get optimum RF signal by combining LPF
and EQ (boost), as shown in Figure 3-4. LPF is defined as -3dB band width without
boost. If the amount of boost is set to a certain value, the gain at cut-off frequency is
as follows:
Gain (at cut-off frequency) = -3dB + Boost amount [dB]
Also, LPF is used as a prefilter for the A/D converter provided in the input stage of
RF block of IC in the post stage (MB75 IC770). Figure 3-4 shows an example.
Figure 3-4. Frequency characteristics (EQ+LPF)
These cut-off frequency and boost amount of LPF are operated by the command
register set via serial interface.
The RF signal processed in this block is output from IC001 FNP%™ and FNN%¡. This
signal is entered to IC001 DIP%£ and DIN%¢ and rectified in full wave, then compared
in the AGC block. Further, it is transferred to the RF signal processor IC765 in the
post stage.
0
1
2
3
4
5
6
7
8
9
10
-15
-10
-5
0
5
10
GAIN(dB)
LPF+EQ
LPF
FREQUENCY (MHz)
– 56 –
(4) Serial interface
Various values of IC001 are set to internal serial port register via serial interface.
Actually, they are set by three signals from the drive control MC IC136. Signals are
SDEN$∞, SDATA$¢, and SCLK$£, and its timing chart is shown in Figure 3-5. Also,
the configuration of serial port register is shown in Figure 3-6.
Figure 3-5. Timing chart
SDEN
SDATA
ADDRESS, 8-BIT
DATA, 8-BIT
SCLK
SDEN
TSENS
TCLK
SCLK
TCKH
TDS
TDH
TCKL
SDATA
(READ)
(READ)
R/W
ADDR 0
ADDR 6
SDATA
(WRITE)
(WRITE)
R/W
ADDR 0
ADDR 6
TTRN
TSENH
TDSKEW
TSENDL
DATA 7
DATA 7
–
57
–
Figure 3-6.
Ser
ial por
t register
DATA BIT MAP
POWER DOWN CONTROL
(PDCR)
FILTER CUTOFF
(FCCR)
FILTER BOOST
(FBCR)
SERVO INPUT GAIN
(SIGR)
RAM SERVO INPUT GAIN
(RSIGR)
FOCUSING GAIN/OFFSET
(FGOR)
TRKING GAIN/OFFSET
(TGOR)
DPT COMP-REF
(DPCR)
MIRR COMP HYS/OFST
(MRCR)
ATTENUATOR/TILT GAIN
(ATGR)
CONTROL A
(CAR)
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
0
ID 2
“1”
F
C
Range
1=max 8M
0=max 16M
TRoffset2
BIT 4
TRoffset2
BIT 3
TRoffset2
BIT 1
FSGAIN
BIT 3
TRGAIN
BIT 3
ComprefD
BIT 3
MRCOMP
HYS-Low
TILT
ON
TMEN
ID 1
“0”
F
C
DAC
BIT 6
F
B
DAC
BIT 6
TRoffset2
BIT 2
TRoffset2
BIT 0
FSGAIN
BIT 2
TRGAIN
BIT 2
ComprefD
BIT 2
MRCOMP
offset
BIT 1
BIT 1
TLGAIN
BIT 2
TMS1
ID 0
“1”
F
C
DAC
BIT 5
F
B
DAC
BIT 5
ABCD
BIT 2
ABCD
RBIT 2
FSGAIN
BIT 1
TRGAIN
BIT 1
ComprefD
BIT 1
MRCOMP
offset
BIT 0
BIT 0
TLGAIN
BIT 1
TMS0
Servo
1=DISABLE
0=ENABLE
F
C
DAC
BIT 4
F
B
DAC
BIT 4
ABCD
BIT 1
ABCD
RBIT 1
FSGAIN
BIT 0
TRGAIN
BIT 0
ComprefD
BIT 0
DPTEQ
BIT 1
TLGAIN
BIT 0
Tracking
SEL
BIT 1
TILT
1=DISABLE
0=ENABLE
F
C
DAC
BIT 3
F
B
DAC
BIT 3
ABCD
BIT 0
ABCD
RBIT 0
FSoffset
BIT 3
TRoffset
BIT 3
ComprefB
BIT 3
DPTEQ
BIT 0
ATT
BIT 3
Tracking
SEL
BIT 0
MIRR
1=DISABLE
0=ENABLE
F
C
DAC
BIT 2
F
B
DAC
BIT 2
EFGH
BIT 2
EFGH
RBIT 2
FSoffset
BIT 2
TRoffset
BIT 2
ComprefB
BIT 2
servoAGC
BIT 2
ATT
BIT 2
LDH/L
APC
1=DISABLE
0=ENABLE
F
C
DAC
BIT 1
F
B
DAC
BIT 1
EFGH
BIT 1
EFGH
RBIT 1
FSoffset
BIT 1
TRoffset
BIT 1
ComprefB
BIT 1
servoAGC
BIT 1
ATT
BIT 1
MIRR
LP2-SEL
RF
1=DISABLE
0=ENABLE
F
C
DAC
BIT 0
F
B
DAC
BIT 0
EFGH
BIT 0
EFGH
RBIT 0
FSoffset
BIT 0
TRoffset
BIT 0
ComprefB
BIT 0
servoAGC
BIT 0
ATT
BIT 0
MIRR
GAIN-Low
REGISTER NAME
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
R/W
A6
A0
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