Sony DVP-NW50 Service Manual ▷ View online
57
DVP-NW50
Pin No.
Pin Name
I/O
Description
49
RSV
—
Not used
50
RSV
—
Not used
51
RSV
—
Not used
52
RSV
—
Not used
53
VSS
—
Ground terminal
54
RSV
—
Not used
55
CVDD
—
Power supply +1.25V
56
CLKOUT2/GP0[2]
—
Not used
57
RSV
—
Not used
58
RSV
—
Not used
59
DVDD
—
Power supply +3.3V
60
VSS
—
Ground terminal
61
RSV
—
Not used
62
RSV
—
Not used
63
RSV
—
Not used
64
RSV
—
Not used
65
RSV
—
Not used
66
RSV
—
Not used
67
CVDD
—
Power supply +1.25V
68
RSV
—
Not used
69
RSV
—
Not used
70
RSV
—
Not used
71
RSV
—
Not used
72
VSS
—
Ground terminal
73
RSV
—
Not used
74
DVDD
—
Power supply +3.3V
75
GP1[6]
—
Not used
76
GP1[7]
—
Not used
77
CVDD
—
Power supply +1.25V
78
VSS
—
Ground terminal
79
GP1[4]
—
Not used
80
GP1[5]
—
Not used
81
GP1[3]
—
Not used
82
GP1[2]
—
Not used
83
GP1[1]
—
Not used
84
GP1[0]
—
Not used
85
RSV
—
Not used
86
CVDD
—
Power supply +1.25V
87
VSS
—
Ground terminal
88
AFSR1
I
LRCLK signal input
89
ACLKR1
I
SCLK signal input
90
DVDD
—
Power supply +3.3V
91
AXR0[15]
I
Sdata signal input
92
AXR0[14]
O
Sdata1 signal output
93
CVDD
—
Power supply +1.25V
94
AXR0[13]
O
Sdata2 signal output
95
AXR0[12]
O
Sdata3 signal output
96
VSS
—
Ground terminal
97
AXR0[11]
O
Sdata4 signal output
58
DVP-NW50
Pin No.
Pin Name
I/O
Description
98
AXR0[10]
I/O
McASP0 TX/RX data (not used)
99
AXR0[9]
I/O
McASP0 TX/RX data (not used)
100
AXR0[8]
I/O
McASP0 TX/RX data (not used)
101
CVDD
—
Power supply +1.25V
102
ACLKX1
O
SCLK signal output
103
DVDD
—
Power supply +3.3V
104
CVDD
—
Power supply +1.25V
105
AMUTE1
I
Mute control signal input
106
VSS
—
Ground terminal
107
AFSX1
O
LRCLK signal output
108
GP0[0]
—
Not used
109
VSS
—
Ground terminal
110
AHCLKX1
I
MCLK signal input
111
GP0[8]
—
Not used
112
AHCLKR1
O
MCASP1 receive high-frequency master clock (not used)
113
GP0[3]
—
Not used
114
CVDD
—
Power supply +1.25V
115
VSS
—
Ground terminal
116
GP0[9]
—
Not used
117
GP0[10]
—
Not used
118
GP0[11]
—
Not used
119
GP0[12]
—
Not used
120
CVDD
—
Power supply +1.25V
121
GP0[13]
—
Not used
122
GP0[14]
—
Not used
123
GP0[15]
—
Not used
124
DVDD
—
Power supply +3.3V
125
RESET
I
Reset signal input
126
VSS
—
Ground terminal
127
CVDD
—
Power supply +1.25V
128
CVDD
—
Power supply +1.25V
129
EMU1
I/O
Select the device functional mode of operation (not used)
130
EMU0
I/O
Select the device functional mode of operation (not used)
131
TDO
I/O
JTAG test-port data out (not used)
132
DVDD
—
Power supply +3.3V
133
TDI
I
JTAG test-port data in (not used)
134
TMS
I
JTAG test-port mode select (not used)
135
TCK
I
JTAG test-port clock (not used)
136
VSS
—
Ground terminal
137
CVDD
—
Power supply +1.25V
138
TRST
I
JTAG test-port reset.
139
RSV
—
Not used
140
VSS
—
Ground terminal
141
CVDD
—
Power supply +1.25V
142
PLLHV
—
Power supply +3.3V
143
RSV
—
Ground terminal
144
CLKIN
I
Clock input
59
DVP-NW50
Pin No.
Pin Name
I/O
Description
1
VRA_PLL
—
Voltage reference for PLL analog supply 1.8 V
2
PLL_FLT_RET
O
PLL external filter return
3
PLL_FLTM
O
PLL negative output
4
PLL_FLTP
I
PLL positive input
5
AVSS
—
Analog ground
6
AVSS_GR
—
Analog ground
7
VRD_PLL
—
Voltage reference for PLL digital supply 1.8 V
8
AVSS_PLL
—
Analog ground for PLL
9
AVDD_PLL
—
3.3V analog power supply for PLL
10
VBGAP
—
Band gap voltage reference
11
RESET
I
System reset input
12
HP_SEL
I
Headphone in/out selector (not used)
13
PDN
I
Power down (not used)
14
MUTE
I
Soft mute of input (not used)
15
DVDD
—
Digital power 3.3V supply for digital core and most of I/O buffers
16
DVSS
—
Digital ground for digital core and most of I/O buffers
17
VR_DPLL
—
Voltage reference for digital PLL supply 1.8 V
18
OSC_CAP
I
Oscillator capacitor
19
XTL_OUT
O
Oscillator output
20
XTL_IN
I
Oscillator input
21
RESERVED
—
Connect to digital ground
22
RESERVED
—
Connect to digital ground
23
RESERVED
—
Connect to digital ground
24
SDA
I/O
I
2
C serial control data interface input / output
25
SCL
I
I
2
C serial control clock input
26
LRCLK
I
Serial audio data
27
SCLK
I
Serial audio data clock (shift clock) SCLKIN
28
SDIN4
I
Serial audio data 4 input
29
SDIN3
I
Serial audio data 3 input
30
SDIN2
I
Serial audio data 2 input
31
SDIN1
I
Serial audio data 1 input
32
PSVC
O
Power supply volume control PWM output
33
VR_DIG
—
Voltage reference for digital core supply 1.8 V
34
DVSS
—
Digital ground
35
DVSS
—
Digital ground
36
DVDD
—
3.3V digital power supply
37
BKND_ERR
I
A backend error sequence
38
DVSS
—
Digital ground
39
VALID
O
Output indicating validity of PWM outputs active high
40
PWM_M_1
O
PWM 1 output (differential –)
41
PWM_P_1
O
PWM 1 output (differential +)
42
PWM_M_2
O
PWM 2 output (differential –)
43
PWM_P_2
O
PWM 2 output (differential +)
44
PWM_M_3
O
PWM 3 output (differential –)
45
PWM_P_3
O
PWM 3 output (differential +)
46
PWM_M_4
O
PWM 4 output (differential –)
47
PWM_P_4
O
PWM 4 output (differential +)
48
VR_PWM
—
Voltage reference for digital PWM core supply 1.8 V
DVD AMP BOARD U401 TAS5508PAGR (DIGITAL AUDIO PROCESSOR)
60
DVP-NW50
Pin No.
Pin Name
I/O
Description
49
PWM_M_7
O
PWM 7 (Line out L) output (differential –)
50
PWM_P_7
O
PWM 7 (Line out L) output (differential +)
51
PWM_M_8
O
PWM 8 (Line out R) output (differential –)
52
PWM_P_8
O
PWM 8 (Line out R) output (differential +)
53
DVSS_PWM
—
Digital ground for PWM
54
DVDD_PWM
—
3.3V digital power supply for PWM
55
PWM_M_5
O
PWM 5 output (differential –) (not used)
56
PWM_P_5
O
PWM 5 output (differential +) (not used)
57
PWM_M_6
O
PWM 6 output (differential –) (not used)
58
PWM_P_6
O
PWM 6 output (differential +) (not used)
59
PWM_HPML
O
PWM left channel headphone (differential –) (not used)
60
PWM_HPPL
O
PWM left channel headphone (differential +) (not used)
61
PWM_HPMR
O
PWM right channel headphone (differential –) (not used)
62
PWM_HPPR
O
PWM right channel headphone (differential +) (not used)
63
MCLK
I
MCLK is a 3.3V clock master clock input
64
RESERVED
—
Connect to digital ground
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