DOWNLOAD Sony DVP-NW50 Service Manual ↓ Size: 7.83 MB | Pages: 65 in PDF or view online for FREE

Model
DVP-NW50
Pages
65
Size
7.83 MB
Type
PDF
Document
Service Manual
Brand
Device
DVD
File
dvp-nw50.pdf
Date
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Sony DVP-NW50 Service Manual ▷ View online

49
DVP-NW50
• IC Pin Function Description
   MAIN BOARD  U1  EP9301-CQZ (CIRRUS) (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
CS7
O
Chip select signal output (not used)
2
CS6
O
FLASH MEMORY chip select signal output
3
CS3
O
Chip select signal output (not used)
4
CS2
O
Chip select signal output (not used)
5
CS1
O
Chip select signal output (not used)
6
AD25
O
Shared address bus out (not used)
7
VDD_RING
—
Power supply   +3.3V
8
GND_RING
—
Ground  terminal
9
AD24
O
Shared address bus out (not used)
10
SDCLK
O
SDRAM clock out
11
AD23
O
Shared address bus out
12
VDD_CORE
—
Power supply   +1.8V
13
GND_CORE
—
Ground  terminal
14
SDWEN
O
SDRAM write enable out
15
SDCSN3
O
SDRAM chip selects out
16
SDCSN2
O
SDRAM chip selects out (not used)
17
SDCSN1
O
SDRAM chip selects out (not used)
18
SDCSN0
O
SDRAM chip selects out (not used)
19
VDD_RING
—
Power supply +3.3V
20
GND_RING
—
Ground terminal
21
RASN
O
SDRAM RAS out
22
CASN
O
SDRAM CAS out
23
DQMN1
O
Shared data mask out
24
DQMN0
O
Shared data mask out
25
AD22
O
Shared address bus out
26
AD21
O
Shared address bus out
27
VDD_RING
—
Power supply +3.3V
28
GND_RING
—
Ground terminal
29
DA15
I/O
Shared data bus in/out
30
AD7
O
Shared address bus out
31
DA14
I/O
Shared data bus in/out
32
AD6
O
Shared address bus out
33
DA13
I/O
Shared data bus in/out
34
VDD_CORE
—
Power supply +1.8V
35
GND_CORE
—
Ground terminal
36
AD5
O
Shared address bus out
37
DA12
I/O
Shared data bus in/out
38
AD4
O
Shared address bus out
39
DA11
I/O
Shared data bus in/out
40
AD3
O
Shared address bus out
41
VDD_RING
—
Power supply +3.3V
42
GND_RING
—
Ground terminal
43
DA10
I/O
Shared data bus in/out
44
AD2
O
Shared address bus out
45
DA9
I/O
Shared data bus in/out
46
AD1
O
Shared address bus out
47
DA8
I/O
Shared data bus in/out
50
DVP-NW50
Pin No.
Pin Name
I/O
Description
48
AD0
O
Shared address bus out
49
VDD_RING
—
Power supply +3.3V
50
GND_RING
—
Ground terminal
51
NC
—
Not used
52
NC
—
Not used
53
VDD_RING
—
Power supply +3.3V
54
GND_RING
—
Ground terminal
55
AD15
O
Shared address bus out
56
DA7
I/O
Shared data bus in/out
57
VDD_CORE
—
Power supply +1.8V
58
GND_RING
—
Ground terminal
59
AD14
O
Shared address bus out
60
DA6
I/O
Shared data bus in/out
61
AD13
O
Shared address bus out
62
 DA5
I/O
Shared data bus in/out
63
AD12
O
Shared address bus out
64
 DA4
I/O
Shared data bus in/out
65
AD11
O
Shared address bus out
66
VDD_RING
—
Power supply +3.3V
67
GND_RING
—
Ground terminal
68
 DA3
I/O
Shared data bus in/out
69
AD10
O
Shared address bus out
70
 DA2
I/O
Shared data bus in/out
71
AD9
O
Shared address bus out
72
 DA1
I/O
Shared data bus in/out
73
AD8
O
Shared address bus out
74
 DA0
I/O
Shared data bus in/out
75
DSRN
O
Data set ready/data carrier detect (not used)
76
DTRN
O
Data terminal ready out
77
TCK
I
JTAG clock in
78
TDI
I
JTAG data in
79
TDO
O
JTAG data out
80
TMS
I
JTAG test mode select
81
VDD_RING
—
Power supply +3.3V
82
GND_RING
—
Ground terminal
83
BOOT1
I
Boot mode select in (not used)
84
BOOT0
I
Boot mode select in (not used)
85
GND_RING
—
Ground terminal
86
NC
—
Not used
87
EECLK
O
Two-wire interface clock output
88
EEDAT
O
Two-wire interface data output
89
ASYNC
I
Frame clock LRCK input
90
VDD_CORE
—
Power supply +1.8V
91
GND_CORE
—
Ground terminal
92
ASDO
O
Transmit data output
93
SCLK1
I/O
SPI bit clock (not used)
94
SFRM1
I/O
SPI frame (not used)
95
SSPRX1
I/O
SPI input (not used)
96
SSPTX1
I/O
SPI output (not used)
51
DVP-NW50
Pin No.
Pin Name
I/O
Description
97
GRLED
O
Green LED drive signal output
98
RDLED
O
Red LED drive signal output
99
VDD_RING
—
Power supply +3.3V
100
GND_RING
—
Ground terminal
101
INT3
I
IR remote signal input
102
INT1
I
Interrupt signal input
103
INT0
I
Remote control signal input
104
RTSN
O
Ready to send signal output
105
USBM0
I/O
USB negative signals (not used)
106
USBP0
I/O
USB positive signals (not used)
107
ABITCLK
I
Bit clock input
108
CTSN
O
Send / transmit enable (not used)
109
RXD0
I
Receive signal in
110
RXD1
O
Receive / IrDA output
111
VDD_RING
—
Power supply +3.3V
112
GND_RING
—
Ground terminal
113
TXD0
O
Transmit signal output
114
TXD1
I
Transmit / IrDA input
115
CGPIO0
O
IR remote signal output
116
GND_CORE
—
Ground terminal
117
PLL_GND
—
PLL ground terminal
118
XTALI
I
Main oscillator input
119
XTALO
O
Main oscillator output
120
PLL_VDD
—
Main oscillator power  +1.8V
121
VDD_CORE
—
Power supply +1.8V
122
GND_RING
—
Ground terminal
123
VDD_RING
—
Power supply +3.3V
124
RSTON
I
Reset signal input
125
PRSTN
I
Power on reset
126
CS0
O
Chip select signal output (not used)
127
GND_CORE
—
Ground terminal
128
VDD_CORE
—
Power supply +1.8V
129
GND_RING
—
Ground terminal
130
VDD_RING
—
Power supply +3.3V
131
ADC 4
O
Not used
132
ADC 3
O
Not used
133
ADC 2
O
Not used
134
ADC 1
O
Tuner stereo signal output
135
ADC 0
O
Tuner tuned signal output
136
ADC_VDD
—
Power supply +3.3V
137
RTCXTALI
I
RTC oscillator input
138
RTCXTALO
O
RTC oscillator output (not used)
139
ADC_GND
—
Ground terminal
140
EGPIO11
O
Tuner SCL signal output
141
EGPIO10
O
LCD CS signal output
142
EGPIO09
O
Monitor child signal output
143
EGPIO08
O
VIDEO switch control signal output
144
EGPIO07
I
CDT signal input from DAR
145
EGPIO06
O
CDT signal output to DAR
52
DVP-NW50
Pin No.
Pin Name
I/O
Description
146
EGPIO05
O
CCLK signal output to DAR
147
EGPIO04
O
CSN signal output to DAR
148
EGPIO03
O
LCD RESET signal output
149
GND_RING
—
Ground terminal
150
VDD_RING
—
Power supply +3.3V
151
EGPIO02
O
LCD RS signal output
152
EGPIO01
O
LCD CLK signal output
153
EGPIO00
O
LCD DATA signal output
154
ARSTN
I
Reset signal input
155
TRSTN
I
JTAG I PD JTAG reset
156
ASDI
I
Primary input
157
USBM2
I/O
USB negative signals (not used)
158
USBP2
I/O
USB positive signals (not used)
159
WAITN
I
SRAM Wait in signal (not used)
160
EGPIO15
I
Key 0 signal input
161
GND_RING
—
Ground terminal
162
VDD_RING
—
Power supply +3.3V
163
EGPIO14
O
PWM1 output
164
EGPIO13
O
Key scan signal output
165
EGPIO12
I
Tuner SDA signal input
166
GND_CORE
—
Ground terminal
167
VDD_CORE
—
Power supply +1.8V
168
FGPIO3
I
Key 2 signal input
169
FGPIO2
I
Key 1 signal input
170
FGPIO1
I
DVDCE signal input
171
GND_RING
—
Ground terminal
172
VDD_RING
—
Power supply +3.3V
173
CLD
O
Collision detect
174
CRS
I
Carrier sense
175
TXERR
O
Transmit error signal output
176
TXEN
O
Transmit enable output
177
MIITXD0
O
Transmit data output
178
MIITXD1
O
Transmit data output
179
MIITXD2
O
Transmit data output
180
MIITXD3
O
Transmit data output
181
TXCLK
I
Transmit clock in
182
RXERR
I
PD receive data error in
183
RXDVAL
I
PD receive data valid in
184
MIIRXD0
I
Receive data in
185
MIIRXD1
I
Receive data in
186
MIIRXD2
I
Receive data in
187
GND_RING
—
Ground terminal
188
VDD_RING
—
Power supply +3.3V
189
MIIRXD3
I
Receive data in
190
RXCLK
I
Receive clock in
191
MDIO
O
Management data out
192
MDC
O
Management data clock out
193
RDN
O
Flash memory read / OE strobe out
194
WRN
O
Flash memory write strobe out
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