Sony DVP-NW50 Service Manual ▷ View online
53
DVP-NW50
Pin No.
Pin Name
I/O
Description
195
AD16
O
Shared address bus out
196
AD17
O
Shared address bus out
197
GND_CORE
—
Ground terminal
198
VDD_CORE
—
Power supply +1.8V
199
HGPIO2
O
Cs signal input
200
HGPIO3
O
Key scan signal output
201
HGPIO4
O
Key scan signal output
202
HGPIO5
O
Key scan signal output
203
GND_RING
—
Ground terminal
204
VDD_RING
—
Power supply +3.3V
205
AD18
O
Shared address bus out
206
AD19
O
Shared address bus out
207
AD20
O
Shared address bus out
208
SDCLKEN
O
SDRAM clock enable out
54
DVP-NW50
Pin No.
Pin Name
I/O
Description
1
MDIO
I/O
Management independent interface (MII) data input/output
2
MDC
I
MII clock input
3
RXD3
O
MII receive data output
4
RXD2
O
MII receive data output
5
RXD1
O
MII receive data output
6
RXD0
O
MII receive data output
7
VDDIO
—
Digital IO 2.5/3.3V tolerant power supply
8
GND
—
Ground terminal
9
RXDV
O
MII receive data valid output
10
RXDCLK
O
MII receive clock output
11
RXER
O
MII receive error output
12
GND
—
Ground terminal
13
VDDC
—
Digital core 2.5V only power supply
14
TXER
I
MII transmit error input
15
TXCLK
O
MII transmit clock output
16
TXEN
I
MII transmit enable input
17
TXD0
I
MII transmit data input
18
TXD1
I
MII transmit data input
19
TXD2
I
MII transmit data input
20
TXD3
I
MII transmit data input
21
COL/RMII
O
MII collision detect output
22
CRS/RMII
O
MII carrier sense output
23
GND
—
Ground terminal
24
VDDIO
—
Digital IO 2.5/3.3V tolerant power supply
25
INT
O
Management interface (MII) interrupt out
26
LED0/TEST
O
Link/Activity LED output
27
LED1/SPD100
O
Speed LED output
28
LED2/DUPLEX
O
Full-duplex LED output
29
LED3/NWAYEN
O
Collision LED output
30
PD
I
Power down signal input
31
VDDRX
—
Analog 2.5V power supply
32
RX–
I
Receive input
33
RX+
I
Receive input
34
FXSD/FXEN
—
Fiber mode enable / signal detect in fiber mode (not used)
35
GND
—
Ground terminal
36
GND
—
Ground terminal
37
REXT
I
External resistor (6.49kW) connects to REXT and ground
38
VDDRCV
—
Analog 2.5V power supply
39
GND
—
Ground terminal
40
TX–
O
Transmit outputs
41
TX+
O
Transmit outputs
42
VDDTX
—
Transmitter 2.5V power supply
43
GND
—
Ground terminal
44
GND
—
Ground terminal
45
XO
O
Xtal feedback
46
XI
I
Crystal oscillator input
47
VDDPLL
—
Analog pll 2.5V power supply
48
RST
I
Reset signal input
MAIN BOARD U26 KSZ8721BL (PHYSICAL LAYER TRANSCEIVER)
55
DVP-NW50
Pin No.
Pin Name
I/O
Description
1
PB5 (MOSI)
O
Serial SPI data output pin for DSP control
2
PB6 (MISO)
I
Serial SPI data input pin for DSP control
3
PB7 (SCK)
O
Serial SPI clock pin for DSP control
4
RESET
I
Reset signal input (connected to vcc)
5
VCC
—
Power supply +3.3V
6
GND
—
Ground terminal
7
XTAL2
O
Output from the inverting oscillator amplifier
8
XTAL1
I
Input to the inverting oscillator amplifier
9
PD0 (RXD)
I
UART input pin for communicate with ARM
10
PD1 (TXD)
O
UART output pin for communicate with ARM
11
PD2 (INT0)
O
5508 mute control (not used)
12
PD3 (INT1)
I
Back end error detect pin (external interrupt pin)
13
PD4 (OC1B)
I
Connected to vcc
14
PD5 (OC1A)
O
Reset signal output
15
PD6 (ICP)
O
Not used
16
PD7 (OC2)
O
PWM output for front LCD back light
17
VCC
—
Power supply +3.3V
18
GND
—
Ground terminal
19
PC0 (SCL)
I/O
I
2
C clock pin for 5508 control
20
PC1 (SDA)
I/O
I
2
C data pin for 5508 control
21
PC2 (TMS)
I
Speaker shut down detect pin
22
PC3 (TCK)
I/O
Not used
23
PC4 (TDO)
O
Test mode pin for mass product
24
PC5 (TDI)
I
Test mode pin for mass product
25
PC6 (TOSC1)
I/O
Not used
26
PC7 (TOSC2)
I/O
Not used
27
AVCC
—
Power supply +3.3V
28
GND
—
Ground terminal
29
AREF
—
Power supply +3.3V
30
PA7 (ADC7)
I/O
Not used
31
PA6 (ADC6)
I/O
Not used
32
PA5 (ADC5)
I/O
Not used
33
PA4 (ADC4)
O
Intercom mode control pin (not used)
34
PA3 (ADC3)
O
Serial SPI data output pin for serial flash control
35
PA2 (ADC2)
I
Serial SPI data input pin for serial flash control
36
PA1 (ADC1)
O
Serial SPI clock pin for serial flash control
37
PA0 (ADC0)
O
Serial SPI select pin for serial flash control
38
VCC
—
Power supply +3.3V
39
GND
—
Ground terminal
40
PB0 (TCK/T0)
O
Reset DSP
41
PB1 (T1)
I/O
Not used
42
PB2 (AIN0/INT2)
O
PSVC signal output
43
PB3 (AIN1/OC0)
I/O
Not used
44
PB4 (SS)
O
Serial SPI select pin for DSP control
DVD AMP BOARD U201 ATMGA32L-8AU (MICRO CONTROLLER)
56
DVP-NW50
Pin No.
Pin Name
I/O
Description
1
GP0[4]
—
Not used
2
GP0[6]
—
Not used
3
CVDD
—
Power supply +1.25V
4
GP0[5]
—
Not used
5
GP0[7]
—
Not used
6
DVDD
—
Power supply +3.3V
7
VSS
—
Ground terminal
8
CVDD
—
Power supply +1.25V
9
AHCLKX0
I/O
McASP0 transmit high-frequency master clock (not used)
10
CVDD
—
Power supply +1.25V
11
VSS
—
Ground terminal
12
ACLKX0
I/O
McASP0 transmit bit clock (not used)
13
ACLKR0
I/O
McASP0 receive bit clock (not used)
14
AXR0[1]
I/O
McASP0 TX/RX data (not used)
15
AFSX0
I/O
McASP0 transmit frame sync (not used)
16
AFSR0
I/O
McASP0 receive frame sync (not used)
17
DVDD
—
Power supply +3.3V
18
AXR0[0]
I/O
McASP0 TX/RX data (not used)
19
VSS
—
Ground terminal
20
FSX1
I
Serial SPI clock signal input
21
DX1
O
Serial SPI data signal output
22
CLKX1
I
Serial SPI select signal input
23
VSS
—
Ground terminal
24
CVDD
—
Power supply +1.25V
25
DR1
I
Serial SPI data signal input
26
VSS
—
Ground terminal
27
CVDD
—
Power supply +1.25V
28
CVDD
—
Power supply +1.25V
29
DVDD
—
Power supply +3.3V
30
VSS
—
Ground terminal
31
CVDD
—
Power supply +1.25V
32
DVDD
—
Power supply +3.3V
33
VSS
—
Ground terminal
34
VSS
—
Ground terminal
35
CVDD
—
Power supply +1.25V
36
VSS
—
Ground terminal
37
CVDD
—
Power supply +1.25V
38
VSS
—
Ground terminal
39
RSV
—
Not used
40
RSV
—
Not used
41
RSV
—
Not used
42
RSV
—
Not used
43
RSV
—
Not used
44
RSV
—
Not used
45
CVDD
—
Power supply +1.25V
46
RSV
—
Not used
47
DVDD
—
Power supply +3.3V
48
VSS
—
Ground terminal
DVD AMP BOARD U301 DA605A004BRFP200 (DIGITAL SIGNAL PROCESSOR)
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