Sony DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 Service Manual ▷ View online
– 28 –
Figure 2-17
28
27
26
IC204 DA CONVERTER
1/2 IC207
L, P, F
1/2 IC206
L, P, F
Q203
FILTER
SWITCH
Q204
FILTER
SWITCH
Q211
MUTE
SW
Q212
MUTE
SW
IC208
HEAD PHONE
BUFFER
J202
CN205
CN202
J202
VIDEO
S-VIDEO
J201
COAX OUT
DIG
OUT
IC210
T201
BUFFER
BUFFER
BUFFER
Q214
DC CONTROL
HP, L
5
3
1
1
3
5
9
11
HP, R
PMUTE
VIDEO_V
VIDEO_Y
VIDEO_C
AU_L
AU_R
L OUT
R OUT
1/2 IC207
BUFFER
1/2 IC206
BUFFER
16
13
21
67
21
67
7
1
2
6
3
1
5
1
3
3
21
1
2
3
15
9
12
10
34
6
5
17
6
IC201 1/3x3
CLOCK BUFFER
2
35
5
1
7
7
1
1
3
4
7
V-MUTE
VS
VIDEO BUFFER
VIDEO_V
VIDEO_Y
VIDEO_C
15
13
10
21
22
21
19
18
16
14
12
10
9
8
7
6
1
1
4
5
AU+12V
AU–12V
P. FAIL
SPDIF
VS
V-MUTE
VIDEO_C
VIDEO_Y
VIDEO_V
SOG3
AUDIO MUTE
D2LT
SCKG3
MAMUTE
AU+5V
POWER CONTROL
IC205
Q202 +9V REG
+9V
–9V
+5V
+5V REG
IC202
MUTE LOGIC
Q205, 210
+7V
+7V REG
Q201 –9V REG
REG DRIVE
Q206, 207, 208
D202, 203
23
25
DAC_BCK
DAC_LRCK
DAC_ADATA
384FS
CN203
CN201
CN204
TO PS-415
ML
MC
MD
LRCK
DATA
BCK
LRCK
DATA
BCK
D1
D2
D3
Q6
CLK
Q5
Q4
XIN
ZERO
L-OUT
R-OUT
IC203
DATA
LATCH
IC211 1/3x3
2-12.
D
VP-S715
A
U-205 Board Block Diagram
– 29 –
2-13. System Control Block
The system controller is composed mainly of the IC805 (HD6437034) SH microcomputer, and
IC807 (CXD8728) large gate array, IC802 (HM62812) 1M SRAM, ICS803 8M FLASH memory,
and IC807 (CXD8747) small gate array, etc. It serves to control the overall servo system.
2-14. Interface Control Block
The interface controller is composed of the IC604 (MB90T678) I/F microcomputer, IC608
(µPD432568) 256K SRAM, IC601 (SN74HC373), and ICS603 external ROM. It sends various
commands to the SH microcomputer based on the switch information from the FL board and
FR board, receives the current information from the SH microcomputer, and displays
on the FL tube display.
– 31 –
– 32 –
IC804
LGA
CXD8728
Vcc=5V
IC805
HD 6437034
System Control
Drive Control
Vcc=5v
IC803
Vcc=5v
IC802
Address
DATA
RD
WR
CSO
CS1
CS6
CS6
WAIT
IRQ6
IRQ0
IRQ7
IRQ3
IRQ2
IRQ3
IRQ2
TxD0
TxD1
TxD1
SCK1
SEL
INT&WAIT
Control
RxDs
MPX
Out put
SIG1
SIG2
SIG2
Address
Decode
Bus
Control
Device
ChipSelect
G, Dir
IWRn
IRDn
SDSPWRn
SDSPRDn
ARPCSn
DCRCSn
AVCSn
ARPINT
DCRINT
ARPWTn
DCRWTn
AVWTn
Group2 RxDs
IWRn
IRDn
SDSPWRn
SDSPRDn
ARPCSn
DCRCSn
AVCSn
ARPINT
DCRINT
ARPWTn
DCRWTn
AVWTn
Group2 RxDs
IFSO
DBSO
IFSI
DBSI
DBSO
IFSI
DBSI
SCKG3
SOG3
SCKG4
SOG4
SCKG4n(DCLK)
SOG3
SCKG4
SOG4
SCKG4n(DCLK)
INT Control
WAIT Control
Expansion
I/O
I/O
Servo Block
AC3
Block
ARP Block
Hsync (from CXD1914)
Advanced HSYNC
(for OSD, DNR, AVDEC)
(for OSD, DNR, AVDEC)
SerialDevise
I/O
T x D0 Sel
R x D0 Sel
Serial
Gp3, 4
CONTROL
LGA
SCKG2PS
AVCK
RxD1 Sel
Group2
ChipSelect
SOG1
SA[0:19]
SD[0:15]
ROM(Flash)8Mbit
RAM (1Mbit)
HM628128
Vcc=5V
IC 506
Vcc=3.3V
IC 806
Vcc=5V
IC 811
Vcc=3.3V
IC 203
Servo DSP
CXD8730
CXD8730
ARP
CXD1865
CXD1865
DECRIPT
CXD1904
CXD1904
AV_DEC
L64020
L64020
RxD1
RxD0
SCKG1
IRQ5
SD [O:7]
SA [1:19]
SA [0:15]
SD [0:7]
SD [O:15]
RD
RD
WR
CS1
SA [0:7]
SD [0:7]
IRDn
IWRn
ARPCSn
ARPINT
ARPWTn
SA0
dir&G Control
BusBuffer
(SGA)
SD [0:7]
SDSPWRn
SDSPRDn
SDSPINT
SA [0:5]
SD [0:7]
IRDn
IWRn
DCRCS
DCRINT
DCRWTn
SA [0:8]
SD [0:7]
IRDn
IWRn
AVCSn
AVINT
AVWTn
CSO
Input
Group3, 4
ChipSelect
S/P Conv
JP SEL
CTS
Diagnostic
Connector
DIAGN
DBSO
DBSI
RxD
TxD
TxD
IFSO
SIO
Ch_m
SI_m
SO_m
Ch_m
SI_m
SO_m
SIO
Ch_n
SO
SCLK
FLCS
FLCS
Ch_n
SO
SCLK
FLCS
FLCS
XSHINT
IC604
CN802
IC207
IC101
SGA
IC807
CXD8747
CXD8747
MB90T678
I/F CON
MB90096A
OSD
SI SCLK CGCS
µ
PD 16311
FL_Cont
SI SCLK FLCS
XIFBSY
IFSI
To
Expansion
I/O
To Expansion
I/O
(Handshake)
I/O
(Handshake)
SOG2PS
HDIN
HCLK
AC3_Dec
MB86342
MB86342
V_Enc
CXD1914Q
CXD1914Q
HDOUT
HCS
SO
XCS
SI
SCK
VSYNC
SOG2PS
SCKG2PS
ACSI
MD
MC
DI
CL
SI
SCK
DI
SK/
DO
CS/
ML
DO
CE
LD
SDATA
SDEN
ACSn
VSI
VCSn
SCKG2PS
IC203~205
DIR
LC89051V
LC89051V
DAC
CXD8750
IC102
SCLK
DDLT
1n~3n
DLT
SSSD
SDEN
DCSn
EESI
ECSn
D2LTn
SSI
(SS133P3720)
DNR
CXD1854Q
EEPROM
BA9020F
BA9020F
MD
MC
ML
DAC
CXD8750
IC006
IC251
IC215
SOG2PS
SH
IC104
IC252
Serial Gp4
Serial Gp3
Serial
Gp2
Gp2
Serial
Gp1
Gp1
Fig. 2-18. System Controller Peripheral Device Control Block Diagram
3.
SERVO BLOCK
3-1.
General Description of Servo Circuits
3-1-1.
Optical Pickup Control
Dedicated optical pickups for DVD and for CD and video CD are provided. The focus and
tracking servo gains are automatically adjusted for every disc loading so that the gains are
constant for every disc to be played.
3-1-2.
Sled Control
Two pickups for DVD and CD/video CD are placed on the same sled, and the position is
controlled with one sled motor. The sled motor is attached with a speed detector utilizing
the Hall element, and a sled speed fluctuation due to mechanical load variations is minimized
by applying the speed servo control (feedback control).
The sled motor used is a DC motor with a brush.
The servo system circuit is used for both DVD and CD.
3-1-3.
Spindle Control
One 3-phase brushless motor controls all disc rotations. The rotation detection pulses (FG:
Frequency Generator) utilizing the Hall element are used for control.
3-1-4.
Tilt Control
The optical pickup is controlled so that the optical axis is perpendicular to the disc; when
DVD is played, it is controlled so that the time axis variation (jitter) of RF signal becomes
minimum.
At the start of DVD play (before RF signal is output), optical sensor detects the tilt angle of
disc and the optical pickup is controlled so that the optical axis is perpendicular to the disc.
The servo system circuit is used for both DVD and CD. At DVD, it always performs tilt
operation, but at CD, it operates only during start-up and stops at the tilt position during
playback.
3-1-5.
Disc Loading and Chucking
One DC motor drives the tray in-out motions, and chucking of disc.
3-1-6.
Disc Judgment
The presence of a disk is judged from the spindle motor spinning start-up time.
Also, the disc size (12cm or 8cm) is judged from the spindle motor speed-up time and disc
data.
– 33 –
Click on the first or last page to see other DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 service manuals if exist.