Sony DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 Service Manual ▷ View online
– 16 –
2-1-1. Attenuation of OP Output Signals
The RF signals (RFP, RFM) output from OP for DVD are attenuated by R066 and
R064 so that they satisfy the input amplitude allowable level of IC006 in the post
stage.
(About 1V
R064 so that they satisfy the input amplitude allowable level of IC006 in the post
stage.
(About 1V
PPD
(*3) for SL (*1) disc. In actual, only the RFP signal is output be-
cause RFM signal is connected to the ground in the OP block.
2-1-2. HPF
Low frequency component of the attenuated RF signal is removed by a high pass
filter (HPF) that cuts off the frequency (about 3.16kHz) determined by the input
impedance of C046, C047, and IC006, then it is entered to the IC001.
filter (HPF) that cuts off the frequency (about 3.16kHz) determined by the input
impedance of C046, C047, and IC006, then it is entered to the IC001.
2-1-3. RF Front End Processing: IC001 SSI33P3720
(1) ATT block
The RF signal entered from IC006 RFP^£ and RFN^¢ is entered to the ATT
block. In this block, this processing is executed to attenuate the signal below
signal amplitude level determined according to the specification (about
200mV
block. In this block, this processing is executed to attenuate the signal below
signal amplitude level determined according to the specification (about
200mV
PPD
, determined depending on AGC input allowable level) in order to
utilize high performance of IC.
After processing, the signal is output from IC006 ATOP^™ and ATON^¡.
After processing, the signal is output from IC006 ATOP^™ and ATON^¡.
ATT: Set to 3/16 for SL disc, or 5/16 for DL (*2) disc.
These are operated by the command register set via serial interface.
(2) AGC block
ATT output IC006 ATOP^™ and ATON^¡ are processed below AGC allow-
able level as mentioned above, then they are AC-coupled by C050 and C051,
and entered respectively to AGC block input IC001 AIP%ª and AIN^º.
The AGC block controls gain of AGC amplifier so that constant input signal
(1V
able level as mentioned above, then they are AC-coupled by C050 and C051,
and entered respectively to AGC block input IC001 AIP%ª and AIN^º.
The AGC block controls gain of AGC amplifier so that constant input signal
(1V
PPD
) is supplied to the IC006 DIP%£ and DIN%¢. The AGC compares
full-wave rectified input signal to IC006 DIP%£ and DIN%¢ with reference
level, and repeats decay and attack while keeping a balance with the product
of current by time so as to attain the optimum gain.
level, and repeats decay and attack while keeping a balance with the product
of current by time so as to attain the optimum gain.
Decay: When input signal to IC006 DIP%£ and DIN%¢ is below 1V
PPD
,
C052 (C
BYP
) is discharged with 4
µ
A decay current. In this case,
AGC amplifier gain gradually increases.
Attack: When input signal to IC006 DIP%£ and DIN%¢ is over 1V
PPD
, C052
(C
BYP
) is charged with 0.18mA attack current. In this case, AGC
amplifier gain gradually decreases.
– 17 –
The input signal to IC006 DIP%£ and DIN%¢ is a signal processed after EQ block
mentioned later.
*1: Single Layer disc
*2: Dual Layer disc
*3: Peak to Peak Differential
(3) EQ block
The EQ block is a programmable equalizer filter differentiator block.
The DVD format is premised on the EQ and requires high frequency signals to be
boosted. This block equalizes RF signal to get optimum RF signal by combining LPF
and EQ (boost), as shown in Figure 2-4. LPF is defined as -3dB band width without
boost. If the amount of boost is set to a certain value, the gain at cut-off frequency is
as follows:
Gain (at cut-off frequency) = -3dB + Boost amount [dB]
Also, LPF is used as a prefilter for the A/D converter provided in the input stage of
RF block of IC in the post stage (MB78 board IC770).
Figure 2-4. Frequency characteristics (EQ+LPF)
These cut-off frequency and boost amount of LPF are operated by the command
register set via serial interface.
The RF signal processed in this block is output from IC006 FNP%™ and FNN%¡. This
signal is entered to IC006 DIP%£ and DIN%¢ and rectified in full wave, then compared
in the AGC block. The RF signal output from IC006 SIG%¶ is then transmitted to the
RF signal processing block IC806 in the post stage.
0
1
2
3
4
5
6
7
8
9
10
-15
-10
-5
0
5
10
GAIN(dB)
LPF+EQ
LPF
FREQUENCY (MHz)
– 18 –
(4) Serial interface
Various values of IC006 are set to internal serial port register via serial interface.
Actually, they are set by three signals from the L G/A IC804. Signals are SDEN$∞,
SDATA$¢, and SCLK$£, and its timing chart is shown in Figure 2-5.
Figure 2-5. Timing chart
SDEN
SDATA
ADDRESS, 8-BIT
DATA, 8-BIT
SCLK
SDEN
TSENS
TCLK
SCLK
TCKH
TDS
TDH
TCKL
SDATA
(READ)
(READ)
R/W
ADDR 0
ADDR 6
SDATA
(WRITE)
(WRITE)
R/W
ADDR 0
ADDR 6
TTRN
TSENH
TDSKEW
TSENDL
DATA 7
DATA 7
– 19 –
2-2.
CD RF Front End
Figure 2-6. TK-47 board RF/CD
The RF signal output from the CD OP is input to IC005 3 and 4, and transmitted to IC806ARP
of the MB-78 board via the amplifier, equalizer.
3
4
30
29
22
21
28
29
28
OPTICAL
BLOCK
CN001
IC005
CXA2555Q
TK-47 board
29
EQ
16
CN005
CDRF
TK-47 board
To MB-78 board
IC806 ARP
P
To MB-78 board
IC806 ARP
P
12
Figure 2-8.
RF envelope waveform at CD disc
TK-47 board CN005
!§
P
500mV
20ns
about 1-1.4Vp-p
range
Figure 2-7.
RF (eye pattern) waveform at CD disc
TK-47 board CN005
!§
P
500mV
500ns
about 1-1.4Vp-p
range
Click on the first or last page to see other DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 service manuals if exist.