Sony DVP-CX777ES Service Manual ▷ View online
121
DVP-CX777ES
•
MB BOARD IC801 CXD9722ATQ (DIGITAL AUDIO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1 to 5
D1 to D5
I/O
Two-way data bus with the SD-RAM
6
VDD
—
Power supply terminal (+3.3V)
7, 8
D6, D7
I/O
Two-way data bus with the SD-RAM
9
VSS
—
Ground terminal
10
WE
O
Write enable signal output to the SD-RAM
11
CAS
O
Column address strobe signal output to the SD-RAM
12
RAS
O
Row address strobe signal output to the SD-RAM
13
CS
O
Chip select signal output to the SD-RAM
14
CLK
O
Clock signal output to the SD-RAM
15
CKE
O
Clock enable signal output to the SD-RAM
16
VDD
—
Power supply terminal (+3.3V)
17 to 22
A11, A10, A0 to A3
O
Address signal output to the SD-RAM
23
VSS
—
Ground terminal
24 to 29
A9 to A4
O
Address signal output to the SD-RAM
30
VSS
—
Ground terminal
31
DRSO
O
DSD data (for rear R-ch) output to the D/A converter
32
DLSO
O
DSD data (for rear L-ch) output to the D/A converter
33
DEXRO
O
Not used
34
DLFEO
O
DSD data (for woofer) output to the D/A converter
35
DCO
O
DSD data (for center) output to the D/A converter
36
VDD
—
Power supply terminal (+3.3V)
37
DRO
O
DSD data (for front R-ch) output to the D/A converter
38
DLO
O
DSD data (for front L-ch) output to the D/A converter
39
VSS
—
Ground terminal
40
DMRO
O
DSD data output for R-ch down mix to the D/A converter
41
DMLO
O
DSD data output for L-ch down mix to the D/A converter
42
VSS
—
Ground terminal
43
VDD
—
Power supply terminal (+3.3V)
44
DLDRO
O
Audio data output to the D/A converter
45
CSWO
O
Audio data (for center and woofer) output to the D/A converter
46
SLSRO
O
Audio data (for rear) output to the D/A converter
47
FLFRO
O
Audio data (for front) output to the D/A converter
48
VSS
—
Ground terminal
49
SPDIFO
O
Digital audio data output terminal
50
TEST1
I
Input terminal for the test
51
TRST
I
Reset signal input from the interface controller “L”: reset
52
TMS
I
Mode selection signal input terminal
53
TCK
I
Clock signal input terminal
54
TDI
I
Serial data signal input from the DSD decoder
55
TDO
O
Serial data signal output to the audio DSP
56
TEST2
I
Input terminal for the test
57
SPDIFI
I
Digital audio data input from the audio DSP
58
VSS
—
Ground terminal
59
LRCKI
I
L/R sampling clock signal input from the audio DSP
60
BCKI
I
Bit clock signal input from the audio DSP
122
DVP-CX777ES
Pin No.
Pin Name
I/O
Description
61
VDD
—
Power supply terminal (+3.3V)
62
VSS
—
Ground terminal
63
DLDRI
I
Audio data input from the audio DSP
64
CSWI
I
Audio data (for center and woofer) input from the audio DSP
65
SLSRI
I
Audio data (for rear) input from the audio DSP
66
FLFRI
I
Audio data (for front) input from the audio DSP
67
TEST3
I
Input terminal for the test
68
CLK512
I
Master clock (27 MHz) input from the clock generator
69
VSS
—
Ground terminal
70
XRST
I
Reset signal input from the system controller “L”: reset
71
VDD
—
Power supply terminal (+3.3V)
72
SCLK
I
Serial clock signal input from the system controller
73
XCS
I
Chip select signal input from the mechanism controller
74
SI
I
Serial data input from the system controller
75
SO
O
Serial data output to the system controller
76
DEXRI
I
Not used
77
DMLI
I
DSD data input for L-ch down mix to the DSD decoder
78
DMRI
I
DSD data input for R-ch down mix to the DSD decoder
79
VSS
—
Ground terminal
80
PHAI
I
Clock signal input from DSD decoder
81
BCKAI
I
Bit clock signal input for DSD data output from DSD decoder
82
DQM
O
Not used
83
DLI
I
DSD data (for front L-ch) input from DSD decoder
84
DRI
O
DSD data (for front R-ch) input from DSD decoder
85
DCI
O
DSD data (for center) input from DSD decoder
86
DLFEI
O
DSD data (for woofer) input from DSD decoder
87
DLSI
O
DSD data (for rear L-ch) input from DSD decoder
88
DRSI
O
DSD data (for rear R-ch) input from DSD decoder
89
VSS
—
Ground terminal
90 to 95
D15 to D10
I/O
Two-way data bus with the SD-RAM
96
VDD
—
Power supply terminal (+3.3V)
97, 98
D9, D8
I/O
Two-way data bus with the SD-RAM
99
GND
—
Ground terminal
100
D0
I/O
Two-way data bus with the SD-RAM
123
DVP-CX777ES
•
MB BOARD IC905 CXD2753R (DSD DECODER)
Pin No.
Pin Name
I/O
Description
1
VSC
—
Ground terminal (for core)
2
XMSLAT
I
Chip select signal input from the system controller
3
MSCK
I
Serial clock signal input from the system controller
4
MSDATI
I
Serial data input from the system controller
5
VDC
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the system controller
7
MSREADY
O
Ready signal output to the system controller
8
XMSDOE
O
Serial data output enable signal output terminal Not used
9
XRST
I
Reset signal input from the system controller “L”: reset
10
SMUTE
I
Soft muting control signal input from the system controller
11
MCKI
I
Master clock signal (33.8688 MHz) input from the clock generator
12
VSIO
—
Ground terminal (for I/O)
13, 14
EXCKO1,
EXCKO2
O
External clock signal output terminal Not used
15
LRCK
O
L/R sampling clock signal output terminal Not used
16
FRAME
O
Not used
17
VDIO
—
Power supply terminal (+3.3V) (for I/O)
18 to 21
MNT0 to MNT7
O
Monitor signal output terminal Not used
22 to 25
TEST0
I
Input terminal for the test (normally: fixed at “L”)
26
TCK
I
Clock signal input terminal
27
TDI
I
Serial data input from the DSP
28
VSC
—
Ground terminal (for core)
29
TDO
O
Serial data output to the digital audio processor
30
TMS
I
Selection signal input terminal
31
TRST
I
Reset signal input from the interface controller “L”: reset
32 to 34 TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDC
—
Power supply terminal (+2.5V) (for core)
36
TESTO
O
Output terminal for the test
37
XBIT
O
Not used
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal Not used
42
VSIO
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used
45
VDIO
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used
48
XSUPAK
O
Supplementary data acknowledge signal output terminal Not used
49
VSC
—
Ground terminal (for core)
50
DSAEXR
O
Not used
51, 52
TESTI
I
Input terminal for the test (normally: fixed at “L”)
53
TESTO
O
Output terminal for the test
54
VDC
—
Power supply terminal (+2.5V) (for core)
55
DSADML
O
DSD data output for L-ch down mix to the digital audio processor
56
DSADMR
O
DSD data output for R-ch down mix to the digital audio processor
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal for DSD data output
“L”: input (slave), “H”: output (master) Fixed at “H” in this set
“L”: input (slave), “H”: output (master) Fixed at “H” in this set
124
DVP-CX777ES
Pin No.
Pin Name
I/O
Description
58
VSDSD
—
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock signal input terminal for DSD data output Not used
60
BCKAO
O
Bit clock signal output for DSD data output to the digital audio processor
61
PHREFI
I
Clock signal input terminal for DSD data output Not used
62
PHREFO
O
Clock signal output to the D/A converter and digital audio processor
63
ZDFL
O
Zero data flag (for front L-ch) detection signal output terminal Not used
64
DSAL
O
DSD data (for front L-ch) output to the digital audio processor
65
ZDFR
O
Zero data flag (for front R-ch) detection signal output terminal Not used
66
DSAR
O
DSD data (for front R-ch) output to the digital audio processor
67
VDDSD
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Zero data flag (for center) detection signal output terminal Not used
69
DSAC
O
DSD data (for center) output to the digital audio processor
70
ZDFLFE
O
Zero data (for woofer) flag detection signal output terminal Not used
71
DSASW
O
DSD data (for woofer) output to the digital audio processor
72
VSDSD
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Zero data flag (for rear L-ch) detection signal output terminal Not used
74
DSALS
O
DSD data (for rear L-ch) output to the digital audio processor
75
ZDFRS
O
Zero data flag (for rear R-ch) detection signal output terminal Not used
76
DSARS
O
DSD data (for rear R-ch) output to the digital audio processor
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
TESTO
O
Output terminal for the test
80
VSC
—
Ground terminal (for core)
81, 82
TESTO
O
Output terminal for the test
83
VDC
—
Power supply terminal (+2.5V) (for core)
84, 85
TESTO
O
Output terminal for the test
86
VSIO
—
Ground terminal (for I/O)
87
TESTO
O
Output terminal for the test
88, 89
TESTI
I
Input terminal for the test (normally: fixed at “L”)
90
VDIO
—
Power supply terminal (+3.3V) (for I/O)
91 to 93
TESTO
O
Output terminal for the test
94
TESTI
I
Input terminal for the test (normally: fixed at “H”)
95
TESTI
I
Input terminal for the test (normally: fixed at “L”)
96
TESTI
I
Input terminal for the test (normally: fixed at “H”)
97
TESTO
O
Output terminal for the test
98
IHOLD
O
Not used
99
VDC
—
Power supply terminal (+2.5V) (for core)
100 to 105
TESTI
I
Input terminal for the test (normally: fixed at “L”)
106
VSIO
—
Ground terminal (for I/O)
107 to 109
TESTI
I
Input terminal for the test (normally: fixed at “L”)
110
VDIO
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
VSIO
—
Ground terminal (for I/O)
116
VSC
—
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection Not used
121
VDC
—
Power supply terminal (+2.5V) (for core)
122
TESTI
I
Input terminal for the test (normally: fixed at “L”)
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