Sony BDP-CX960 Service Manual ▷ View online
BDP-CX960
77
MB-124-MEGA-SM BOARD IC310 SN0608006PWPR (POWER CONTROL2)
Pin No.
Pin Name
I/O
Description
1
VLDOIN
I
Power supply input terminal (for VTT LDO)
2
VTT
O
VTT LDO output terminal
3
VTTGND
-
Ground terminal (for VTT LDO)
4
VTTSNS
I
VTT voltage detection signal input terminal
5
GND
-
Ground terminal
6
MODE
I
Electrical discharge mode setting terminal Not used
7
VTTREF
O
Reference voltage output terminal
8
COMP
O
Transformer conductance amplifi er output terminal for phase compensation
9
VDDQSNS
I
VDDQ reference voltage input terminal
10
VDDQSET
I
VDDQ output voltage setting terminal
11
S3
I
S3 signal input terminal
12
S5
I
S5 signal input terminal
13
PGOOD
O
Power good open drain output terminal Not used
14
V5IN
I
+5V power supply input terminal
15
CS
I
Current detection comparator input terminal
16
PGND
-
Ground terminal (for rectifi cation MOSFET driver)
17
DRVL
O
Rectifi cation MOSFET gate drive signal output terminal
18
LL
I
Return terminal of switching MOSFET driver
19
DRVH
O
Switching MOSFET gate drive signal output terminal
20
VBST
I
Boot strap voltage input terminal for switching MOSFET driver
BDP-CX960
78
Pin No.
Pin Name
I/O
Description
1
PPON1
O
Power supply control signal output terminal Not used
2
OCI20
I
Over current status input terminal Not used
3
VSS
-
Ground terminal
4
PPON2
O
Power supply control signal output terminal Not used
5
OCI30
I
Over current status input terminal Not used
6
PPON3
O
Power supply control signal output terminal Not used
7
VDD
-
Power supply terminal (+3.3V)
8
VCCRST0
I
Reset signal input terminal “L”: reset Fixed at “H” in this set
9
PME0
O
PME signal output terminal Not used
10
NC
-
Not used
11
PCLK
I
33 MHz clock signal input terminal
12
VSS
-
Ground terminal
13
VBBRST0
I
Reset signal input from the BD decoder “L”: reset
14
INTA0
O
Interrupt signal output to the BD decoder
15
GNT0
I
Grant signal input from the BD decoder
16
REQ0
O
Request signal output to the BD decoder
17
AD31
I/O
Two-way address and data bus with the BD decoder
18
VDD
-
Power supply terminal (+3.3V)
19, 20
AD30, AD29
I/O
Two-way address and data bus with the BD decoder
21
VSS
-
Ground terminal
22 to 26
AD28 to AD24
I/O
Two-way address and data bus with the BD decoder
27
VDD
-
Power supply terminal (+3.3V)
28
CBE30
I/O
Command and byte enable signal input/output with the BD decoder
29
IDSEL
I
Initialization device selection signal input from the BD decoder
30
VDD15
-
Power supply terminal (+1.5V)
31
VSS
-
Ground terminal
32 to 36
AD23 to AD19
I/O
Two-way address and data bus with the BD decoder
37
VDD
-
Power supply terminal (+3.3V)
38
AD18
I/O
Two-way address and data bus with the BD decoder
39
VSS
-
Ground terminal
40, 41
AD17, AD16
I/O
Two-way address and data bus with the BD decoder
42
CBE20
I/O
Command and byte enable signal input/output with the BD decoder
43
FRAME0
I/O
Frame signal input/output with the BD decoder
44
IRDY0
I/O
Initiator ready signal input/output with the BD decoder
45
VSS
-
Ground terminal
46
NC
-
Not used
47
TRDY0
I/O
Target ready signal input/output with the BD decoder
48
VDD
-
Power supply terminal (+3.3V)
49
DEVSEL0
I/O
Device selection signal input/output with the BD decoder
50
STOP0
I/O
Stop signal input/output with the BD decoder
51
PERR0
I/O
Parity error signal input/output with the BD decoder
52
SERR0
I/O
System error signal input/output with the BD decoder
53
PAR
I/O
Parity signal input/output with the BD decoder
54
VSS
-
Ground terminal
55
CBE10
I/O
Command and byte enable signal input/output with the BD decoder
56
AD15
I/O
Two-way address and data bus with the BD decoder
57
VDD
-
Power supply terminal (+3.3V)
58, 59
AD14, AD13
I/O
Two-way address and data bus with the BD decoder
60
VSS
-
Ground terminal
61
VDD15
-
Power supply terminal (+1.5V)
62 to 64
AD12 to AD10
I/O
Two-way address and data bus with the BD decoder
65
VDD
-
Power supply terminal (+3.3V)
66, 67
AD9, AD8
I/O
Two-way address and data bus with the BD decoder
68
CBE00
I/O
Command and byte enable signal input/output with the BD decoder
69
NC
-
Not used
70
AD7
I/O
Two-way address and data bus with the BD decoder
71
VSS
-
Ground terminal
72 to 74
AD6 to AD4
I/O
Two-way address and data bus with the BD decoder
MB-124-MEGA-SM BOARD IC602
μPD720102GC-YEB-E2-A (USB INTERFACE)
BDP-CX960
79
Pin No.
Pin Name
I/O
Description
75
VDD
-
Power supply terminal (+3.3V)
76 to 79
AD3 to AD0
I/O
Two-way address and data bus with the BD decoder
80
VSS
-
Ground terminal
81
XT1/SCLK
I
System clock input terminal (30 MHz)
82
NC
-
Not used
83
XT2
O
System clock output terminal (30 MHz)
84
VDD
-
Power supply terminal (+3.3V)
85
CRUN0
I/O
Clock run signal input/output terminal Not used
86
SMI0
O
System management interrupt signal output terminal Not used
87
VSS
-
Ground terminal
88
SRCLK
O
Serial ROM clock signal output terminal Not used
89
SRMOD
I
Serial ROM input enable signal input terminal Not used
90
SRDTA
I/O
Two-way serial ROM data bus terminal Not used
91
CLKSEL
I
Clock frequency selection signal input terminal “L”: crystal oscillation (30 MHz) input,
“H”: External clock (48 MHz) signal input Fixed at “L” in this set
“H”: External clock (48 MHz) signal input Fixed at “L” in this set
92
HSMODE
I
Hyper speed transfer mode selection signal input terminal
“H”: Hyper speed transfer mode on Fixed at “L” in this set
“H”: Hyper speed transfer mode on Fixed at “L” in this set
93
TESTEN
I
Test enable terminal Not used
94
AVSS(R)
-
Ground terminal
95
RREF
-
Reference resistor connection terminal
96
AVDD33
-
Power supply terminal (+3.3V) (analog system)
97
AVDD15
-
Power supply terminal (+1.5V) (analog system)
98
AVSS
-
Ground terminal (analog system)
99
VSS
-
Ground terminal
100
VDD15
-
Power supply terminal (+1.5V)
101
DM1
I/O
Two- way USB data (negative) bus terminal Not used
102
DP1
I/O
Two- way USB data (positive) bus terminal Not used
103, 104
VSS
-
Ground terminal
105
DM2
I/O
Two- way USB data (negative) bus with the USB connector
106
DP2
I/O
Two- way USB data (positive) bus with the USB connector
107, 108
VDD
-
Power supply terminal (+3.3V)
109
DM3
I/O
Two- way USB data (negative) bus terminal Not used
110
DP3
I/O
Two- way USB data (positive) bus terminal Not used
111
VSS
-
Ground terminal
112
VDD
-
Power supply terminal (+3.3V)
113
NC
-
Not used
114
VSS
-
Ground terminal
115
VDD15OUT
O
Power supply output terminal (+1.5V )
116, 117
VDD
-
Power supply terminal (+3.3V)
118, 119
TEST4, TEST3
I
Test mode terminal Not used
120
OCI10
I
Over current status input terminal Not used
BDP-CX960
80
MB-124-MEGA-SM BOARD IC8001 LAN8700C-AEZG-CTI (ETHERNET INTERFACE)
Pin No.
Pin Name
I/O
Description
1
nINT/TX_ER/TXD4
I/O
Not used
2
MDC
I
Management clock signal input from the BD decoder
3
CRS
I/O
Not used
4
MDIO
I/O
Two-way management data bus with the BD decoder
5
nRST
I
Reset signal input from the system controller “L”: reset
6
TX_EN
I
Enable signal input from the BD decoder
7
VDD33
-
Power supply terminal (+3.3V)
8
VDD_CORE
-
Power supply terminal (+1.8V) Not used
9
SPEED100
I/O
Not used
10
LINK
I/O
Not used
11
ACTIVITY
I/O
Not used
12
FDUPLEX
I/O
Not used
13
XTAL2
O
System clock output terminal Not used
14
REFCLK
I
System clock input terminal (50 MHz)
15, 16
RXD3, RXD2
O
Serial data output terminal Not used
17, 18
RXD1, RXD0
O
Serial data output to the BD decoder
19
RX_DV
O
Not used
20
RX_CLK
O
Not used
21
RX_ER
O
Error signal output to the BD decoder
22
TX_CLK
O
Not used
23, 24
TXD0, TXD1
I
Serial data input from the BD decoder
25
VDDIO
-
Power supply terminal (+3.3V)
26, 27
TXD2, TXD3
I
Serial data input terminal Not used
28
TXN
O
Serial data (negative) output to the ethernet connector
29
TXP
O
Serial data (positive) output to the ethernet connector
30
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
31
RXN
I
Serial data (negative) input from the ethernet connector
32
RXP
I
Serial data (positive) input from the ethernet connector
33
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
34
EXRES1
I
Reference resistor connection terminal
35
VDDA3.3
-
Power supply terminal (+3.3V) (analog system)
36
CRS_DV
O
Carrier sense output to the BD decoder
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