Sony AVD-C700ES Service Manual ▷ View online
45
AVD-C700ES
Pin No.
Pin Name
I/O
Pin Description
60
MUTE_2D
O
Muting ON/OFF control signal output to focus/tracking coil driver, spindle/sled motor
driver IC.
61
SLED
I
Sled motor servo drive PWM signal input from CD decoder, digital servo processor IC.
62
FG
I
Spindle motor control signal input
63
SP_ON
O
Muting ON/OFF control signal output to focus/tracking coil driver, spindle/sled motor
driver IC.
64
JIT
I
Jitter signal input
65
TE
I
Tracking error signal input
66
PI
I
Pull in signal input
67
FE
I
Focus error signal input
68
AVSS
—
Ground pin
69
AVREF
I
Reference voltage input (for A/D converter)
70
AVDD
—
Power supply pin (+3.3 V) (for A/D converter)
71
GFS_CD
I
Guard frame sync signal input from CD decoder, digital servo processor IC.
72
SCLK_CD
O
SENSE serial data reading clock signal output to CD decoder, digital servo processor
IC.
73
TSD-M
O
Thermal shut down signal output to focus/tracking coil driver, spindle/sled motor
driver IC.
74
FOK_CD
I
Focus OK signal input from CD decoder, digital servo processor IC.
75
LOCK_CD
I
GFS is sampled by 460 Hz. (H input when GFS is H)
76
LDSEL
O
Laser diode selection signal output
77
SACD/DVD
O
SACD/DVD selection signal output
78
I2C_SIO
I/O
Communication data bus signal input/output
79
I2C_SCL
I/O
Communication data reading clock signal input/output
80
RXD
I
Serial data input
81
TXD
O
Serial data output
82
SDCLK_RF
O
Serial data transfer clock signal output
83
SDATA_RF
I/O
Two-way data bus signal input/output
84
XWR
O
Write strobe signal output to DVD decoder IC.
85
XRD
O
Read strobe signal output to DVD decoder IC.
86
(PWE)
—
Not used (Fixed at H)
87
VDD
—
Power supply pin (+3.3 V)
88
VSS
—
Ground pin
89 to 96
A0 to A7
O
Address signal output to DVD decoder IC.
97
A8
O
Power save control signal output to focus/tracking coil driver, spindle/sled motor
driver IC.
98
XDRST
O
Reset signal output to CD decoder, digital servo processor IC.
99
EEP_CS
O
Write protect signal output to EEPROM IC.
100
EEP_CLK
O
Clock signal output to EEPROM IC.
46
AVD-C700ES
• IC1041 ZIVA-5P-C2F (DVD SYSTEM PROCESSOR) (MB Board (9/12))
Pin No.
Pin Name
I/O
Pin Description
1
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
2
HA1
I/O
Address bus signal input/output
3 to 11
HAD15 to HAD7
I/O
Data bus (address signal multiplexed) signal input/output
12
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
13
GNDP
—
Ground pin (I/O signal)
14 to 19
HAD6 to HAD1
I/O
Data bus (address signal multiplexed) signal input/output
20
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
21
GNDP
—
Ground pin (I/O signal)
22
HAD0
I/O
Data bus (address signal multiplexed) signal input/output
23
HDTACK
I/O
Acknowledge signal input/output for host data transfer
24
HIRQ0
I
Interrupt signal input
25
WEH.UDS
I/O
Host upper data strobe signal input/output
26
WEL.LDS
I/O
Host lower data strobe signal output
27
HREAD
I/O
Read/write strobe signal input/output
28
GPIO0(1)/JIGMODE
I/O
Jig detection port
29
GND
—
Ground pin (inside core)
30
VDD
—
Power supply pin (+1.8 V) (inside core)
31
GND25
—
Ground pin (SDRAM I/O signal)
32
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
33 to 42
MA9 to MA0
O
SDRAM address bus signal output to 128 Mbit SD-RAM IC.
43
GND25
—
Ground pin (SDRAM I/O signal)
44
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
45, 46
MA10, MA11
O
SDRAM address bus signal output to 128 Mbit SD-RAM IC.
47, 48
BA1, BA0
O
SDRAM bank select signal output to 128 Mbit SD-RAM IC.
49
MCS0
O
SDRAM chip select signal output to 128 Mbit SD-RAM IC.
50
MCS1
O
Not used. (Open)
51
MRAS
O
SDRAM row address strobe signal output to 128 Mbit SD-RAM IC.
52
MCAS
O
SDRAM column address strobe signal output to 128 Mbit SD-RAM IC.
53
MWE
O
SDRAM write enable signal output to 128 Mbit SD-RAM IC. (H: read, L: write)
54
GND25
—
Ground pin (SDRAM I/O signal)
55
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
56
MCLK
O
SDRAM clock signal output to 128 Mbit SD-RAM IC.
57 to 60
MD0 to MD3
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
61
GND25
—
Ground pin (SDRAM I/O signal)
62
MDQM0
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
63
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
64 to 71
MD4 to MD11
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
72
GND25
—
Ground pin (SDRAM I/O signal)
73
MDQM1
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
74
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
75 to 78
MD12 to MD15
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
79
GND
—
Ground pin (inside core)
80
VDD
—
Power supply pin (+1.8 V) (inside core)
81 to 84
MD16 to MD19
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
85
GND25
—
Ground pin (SDRAM I/O signal)
86
MDQM2
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
87
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
88 to 95
MD20 to MD27
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
96
GND25
—
Ground pin (SDRAM I/O signal)
97
MDQM3
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
98
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
99 to 102
MD28 to MD31
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
47
AVD-C700ES
Pin No.
Pin Name
I/O
Pin Description
103
GND25
—
Ground pin (SDRAM I/O signal)
104
VDD25
—
Power supply pin (+3.3 V) (SDRAM I/O signal)
105
VCLK
I/O
System clock signal input/output
106
VDATA7
O
Video data 7 signal output
107
VDATA6
O
Video data 6 signal output
108
VDATA5
O
Video data 5 signal output
109
VDATA4
O
Video data 4 signal output
110
VDATA3
O
Video data 3 signal output
111
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
112
GNDP
—
Ground pin (I/O signal)
113
VDATA2
O
Video data 2 signal output
114
VDATA1
O
Video data 1 signal output
115
VDATA0
O
Video data 0 signal output
116
HIRQ2
I
Busy signal input from EEPROM IC.
117
VDAC_4B
—
Video DAC bias bit 4 (Connect to ground)
118
VDAC_VDD4
—
Power supply pin (+3.3 V) (Video DAC 4)
119
VDAC_4
O
VDAC output 4
120
VDAC_3B
—
Video DAC bias bit 3 (Connect to ground)
121
VDAC_VDD3
—
Power supply pin (+3.3 V) (Video DAC 3)
122
VDAC_3
O
VDAC output 3
123
VDAC_2B
—
Video DAC bias bit 2 (Connect to ground)
124
VDAC_VDD2
—
Power supply pin (+3.3 V) (Video DAC 2)
125
VDAC_2
O
VDAC output 2
126
VDAC_1B
—
Video DAC bias bit 1 (Connect to ground)
127
VDAC_VDD1
—
Power supply pin (+3.3 V) (Video DAC 1)
128
VDAC_1
O
VDAC output 1
129
VDAC_0B
—
Video DAC bias bit 0 (Connect to ground)
130
VDAC_VDD0
—
Power supply pin (+3.3 V) (Video DAC 0)
131
VDAC_0
O
VDAC output 0
132
VDAC_DVSS
—
Ground pin (Video DAC digital system)
133
VDAC_DVDD
—
Power supply pin (+3.3 V) (Video DAC digital system)
134
VDAC_REFVDD
—
Power supply pin (+3.3 V) (Video DAC reference)
135
VDAC_REF
I
Reference voltage input (for Video DAC)
136
VDAC_REFVSS
—
Ground pin (Video DAC reference)
137
XVSS
—
Ground pin (crystal oscillator)
138
XOUT
O
Not used. (Open)
139
XIN
I
Crystal oscillation signal input
140
XVDD
—
Power supply pin (+3.3 V) (crystal oscillator)
141
AVSS2
—
Ground pin (analog PLL)
142, 143
AVDD2, AVDD1
—
Power supply pin (+3.3 V) (analog PLL)
144
AVSS1
—
Ground pin (analog PLL)
145
VDD
—
Power supply pin (+1.8 V) (inside core)
146
GND
—
Ground pin (inside core)
147
XCK
O
Audio system clock signal output Not used. (Open)
148
LRCK
O
LRCK signal output Not used. (Open)
149
BCK
O
BCK signal output Not used. (Open)
150
GA_RST
O
GA reset signal output
151
GPIO4 (2)
O
Video reset signal output to video encoder IC
152
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
153
GNDP
—
Ground pin (I/O signal)
154
VS
O
S1 signal output
155
V-SEL2
O
Fixed at L in this set.
156
IEC958
O
S/PDIF signal output
48
AVD-C700ES
Pin No.
Pin Name
I/O
Pin Description
157
GPIO4 (8)
I
Not used. (Open)
158
GPIO4 (7)
I
Not used. (Open)
159
GPIO4 (6)
I
Not used. (Open)
160
I2C_CL
I/O
I2C clock bus signal input from/output to mechanism control IC.
161
I2C_DA
I/O
I2C data bus signal input from/output to mechanism control IC.
162
CS_EEPROM
O
Chip select signal output to EEPROM IC.
163
RXD1
I
Serial data input from check jig
164
TXD1
O
Serial data output to check jig
165
WC_EEPROM
O
Write control signal output to EEPROM IC.
166
GNDP
—
Ground pin (I/O signal)
167
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
168 to 171
SDDATA7 to SDDATA4
I
SDBUS data input from DVD decoder IC.
172
GND
—
Ground pin (inside core)
173
VDD
—
Power supply pin (+1.8 V) (inside core)
174 to 177
SDDATA3 to SDDATA0
I
SDBUS data input from DVD decoder IC.
178
SDREQ
O
SDBUS data request signal output to DVD decoder IC.
179
SDEN
I
SDBUS data enable signal input from DVD decoder IC.
180
GNDP
—
Ground pin (I/O signal)
181
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
182
SDERROR
I
SDBUS data error signal input from DVD decoder IC.
183
SDCLK
I
SDBUS data clock signal input from DVD decoder IC.
184
HIRQ1
I
Interrupt signal input from mechanism control IC.
185
DRVCLK
I
Serial data clock signal input from mechanism control IC.
186
DRVTX
I
Serial data input from mechanism control IC and EEPROM IC.
187
DRVRX
O
Serial data output to mechanism control IC and EEPROM IC.
188
DRVRDY
I
Ready signal input from mechanism control IC.
189
VNW
—
Power supply for 5 V tolerance voltage input
190
ALE
O
Latch enable signal output for address data demux.
191
RST_SPC
O
Reset signal output to mechanism control IC.
192
HCS3
O
Not used. (Open)
193
HCS2
O
Chip select signal output
194
HCS1/XGACS
I/O
Chip select signal input/output
195
HCS0
O
Chip select signal output
196
VDDP
—
Power supply pin (+3.3 V) (I/O signal)
197
TRST
I
Reset signal input
198
TDO
O
Data output
199
TDI
I
Data input
200
TMS
I
TMS signal input
201
TCK
I
TCK signal input
202
RESET
I
ZIVA reset signal input
203
BUS CLK
I/O
Not used. (Open)
204
GND
—
Ground pin (inside core)
205
VDD
—
Power supply pin (+1.8 V) (inside core)
206, 207
HA3, HA2
I/O
Address bus signal input/output
208
GNDP
—
Ground pin (I/O signal)
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