Sony AVD-C700ES Service Manual ▷ View online
37
AVD-C700ES
Pin No.
Pin Name
I/O
Pin Description
51
AVSS1
—
Ground pin (analog system)
52
CLTV
I
Internal VCO control voltage input
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge pump output for master PLL
56
AVDD1
—
Power supply pin (+3.3 V) (analog system)
57
BIAS
I
Asymmetry circuit constant current input terminal
58
VCTL
I
VCO control voltage input for the wideband EFM PLL
59
V16M
O
VCO oscillation output for the wideband EFM PLL Not used. (Open)
60
VPCO
O
Charge pump output for the wideband EFM PLL
61
DVDD2
—
Power supply pin (+3.3 V) (digital system)
62
ASYE
I
Asymmetry circuit on/off control signal input “L”: off, “H”: on
63
MD2
I
Digital out on/off control signal input from mechanism controller IC
“L”: digital out off, “H”: digital out on
64
DOUT
O
Digital audio signal output
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to DVD decoder IC
66
PCMD
O
Serial data output to DVD decoder IC
67
BCK
O
Bit clock signal (2.8224 MHz) output to DVD decoder IC
68
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used. (Open)
69
CD-DVD-XTSL
I
Input for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688 MHz
70
DVSS2
—
Ground pin (digital system)
71
XTAI
I
System clock input (33.8688 MHz)
72
XTAO
O
System clock output (33.8688 MHz) Not used. (Open)
73
SOUT
O
Serial data output Not used. (Open)
74
SOCK
O
Serial data reading clock signal output Not used. (Open)
75
XOLT
O
Serial data latch pulse signal output Not used. (Open)
76
SQSO
O
Subcode Q data output to mechanism controller IC
77
SQCK
I
Subcode Q data reading clock signal input from mechanism controller IC
78
SCSY
I
Input for resynchronism of guard subcode sync (S0+S1)
79
SBSO
O
Subcode serial data output to DVD decoder IC
80
EXCK
I
Subcode serial data reading clock signal input to DVD decoder IC
38
AVD-C700ES
• IC1027 TMC57929PGF-RDP (DVD DECODER) (MB Board (6/12))
Pin No.
Pin Name
I/O
Pin Description
1, 2
D5, D6
I/O
Two-way data bus signal input from/output to mechanism control IC.
3
VSS
—
Ground pin
4
D7
I/O
Two-way data bus signal input from/output to mechanism control IC.
5
A0
I/O
Address signal input from/output to mechanism control IC.
6
VDD
—
Power supply pin (+3.3 V)
7
A1
I/O
Address signal input from/output to mechanism control IC.
8
VDD5V
—
Power supply pin (+5 V)
9 to 14
A2 to A7
I/O
Address signal input from/output to mechanism control IC.
15
VSS
—
Ground pin
16
XWAIT
O
Not used. (Open)
17
XRD
I
Read strobe signal input from mechanism control IC.
18
XWR
I
Write strobe signal input from mechanism control IC.
19
XCS
I
Chip select signal input from mechanism control IC.
20, 21
XINT0, XINT1
O
Interrupt signal output to mechanism control IC.
22
VDD
—
Power supply pin (+3.3 V)
23
XHRS
I
Not used. (Open)
24
HDB7
I/O
Stream data input from/output to DVD system processor IC.
25
VSS
—
Ground pin
26
HDB8
I/O
Error flag signal input from/output to DVD system processor IC.
27
HDB6
I/O
Stream data input from/output to DVD system processor IC.
28
VDDS
—
Power supply pin (+5 V)
29
HDB9
I/O
Not used. (Open)
30
HDB5
I/O
Stream data input from/output to DVD system processor IC.
31
HDBA
I/O
Not used. (Open)
32
HDB4
I/O
Stream data input from/output to DVD system processor IC.
33
VSS
—
Ground pin
34
HDBB
I/O
Not used. (Open)
35
HDB3
I/O
Stream data input from/output to DVD system processor IC.
36
VDD
—
Power supply pin (+3.3 V)
37
HDBC
I/O
Not used. (Open)
38
VDDS
—
Power supply pin (+5 V)
39
HDB2
I/O
Stream data input from/output to DVD system processor IC.
40
HDBD
I/O
Not used. (Open)
41
HDB1
I/O
Stream data input from/output to DVD system processor IC.
42
VSS
—
Ground pin
43
HDBE
I/O
Not used. (Open)
44
HDBO
I/O
Stream data input from/output to DVD system processor IC.
45
HDBF
I/O
Not used. (Open)
46
HDRQ
O
Serial data effect flag signal output to DVD system processor IC.
47
VDDS
—
Power supply pin (+5 V)
48
XHWR
I
Serial data transfer clock signal input from DVD system processor IC.
49
XHRD
I
Serial data transfer clock signal input from DVD system processor IC.
50
VDD
—
Power supply pin (+3.3 V)
51
REDY
O
Not used. (Fixed at H.)
52
VSS
—
Ground pin
53
XHAC
I
Serial data request signal input from DVD system processor IC. (DVD mode)
54
HINT
I/O
Not used. (Fixed at H.)
55
XS16
I
Not used. (Fixed at H.)
56
HA1
I
Not used. (Fixed at H.)
57
XPDI
I/O
Not used. (Fixed at H.)
58
VDDS
—
Power supply pin (+5 V)
59, 60
HA0, HA2
I
Not used. (Fixed at H.)
39
AVD-C700ES
Pin No.
Pin Name
I/O
Pin Description
61
VSS
—
Ground pin
62, 63
HCS0, HCS1
I
Not used. (Open)
64
VDD
—
Power supply pin (+3.3 V)
65
DASP
I/O
Not used. (Fixed at H.)
66 to 69
MDB0 to MDB3
I/O
Two-way data bus signal input from/output to 16Mbit D-RAM IC.
70
VSS
—
Ground pin
71
MDB4
I/O
Two-way data bus signal input from/output to 16Mbit D-RAM IC.
72
VDD5V
—
Power supply pin (+5 V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus signal input from/output to 16Mbit D-RAM IC.
76
XMWR
O
Write enable signal output to 16Mbit D-RAM IC.
77
VDD
—
Power supply pin (+3.3 V)
78
XRAS
O
Row address strobe signal output to 16Mbit D-RAM IC.
79, 80
MA0, MA1
O
Address signal output to 16Mbit D-RAM IC.
81
VSS
—
Ground pin
82 to 87
MA2 to MA7
O
Address signal output to 16Mbit D-RAM IC.
88
VDD
—
Power supply pin (+3.3 V)
89
MA8
O
Address signal output to 16Mbit D-RAM IC.
90
VSS
—
Ground pin
91
MA9/mnt0
O
Address signal output to 16Mbit D-RAM IC.
92
MA10/mnt1
O
EEPROM ready signal output to mechanism control IC.
93
MA11/mnt2
O
Address signal output to 16Mbit D-RAM IC.
94
XMOE
O
Output enable signal output to 16Mbit D-RAM IC.
95
XCAS
O
Column address strobe signal output to 16Mbit D-RAM IC.
96, 97
MDB8, MDB9
I/O
Two-way data bus signal input from/output to 16Mbit D-RAM IC.
98
VSS
—
Ground pin
99
MDBA
I/O
Two-way data bus signal input from/output to 16Mbit D-RAM IC.
100
VDD
—
Power supply pin (+3.3 V)
101, 102
MDBB, MDBC
I/O
Two-way data bus signal input from/output to 16Mbit D-RAM IC.
103
VDD5V
—
Power supply pin (+5 V)
104 to 106
MDBD to MDBF
I/O
Two-way data bus signal input from/output to 16Mbit D-RAM IC.
107
GFS
O
Guard frame sync signal output to mechanism control IC.
108
VSS
—
Ground pin
109
APE0
O
Absolute phase error signal output
110
VDD
—
Power supply pin (+3.3 V)
111
DASY0
O
RF binary signal output
112
GNDA5
—
Ground pin
113, 114
ASF1, ASF2
O
Filter connected pin for selection the constant asymmetry compensation.
115
DASY1
I
Analog signal input after integrated from the RF binary signal.
116
RFDCC
I
Input pin for adjusting DC cut high-pass filter for RF signal.
117
RFIN
I
RF signal input
118, 119
VCCA5, VCCA4
—
Power supply pin (+3.3 V)
120
VCOR1
I
VCO oscillating range setting resistor connected
121
VCOIN
I
VCO input
122, 123
GNDA4, GNDA3
—
Ground pin
124
LPF5
O
Inverted signal output to operation amplifier from PLL loop filter.
125
VC1
I
Middle point voltage (+1.65 V) input
126, 127
LPF1, LPF2
I
Inverted signal input from operation amplifier from PLL loop filter.
128, 129
VCCA3, VCCA2
—
Power supply pin (+3.3 V)
130
PD0
O
Signal output to charge pump for phase comparator.
131
PDHVCC
O
Middle point voltage output to RF PLL.
132
FDO
O
Signal output to charge pump for frequency comparator.
133, 134
GNDA2, GNDA1
—
Ground pin
40
AVD-C700ES
Pin No.
Pin Name
I/O
Pin Description
135
SPO
O
Spindle motor control signal output to focus/tracking coil driver, spindle/sled motor
driver IC.
136
VC2
I
Middle point voltage (+1.65 V) input
137
MDIN2
I
Spindle motor servo drive signal input
138
MDIN1
I
MDP input
139
VCCA1
—
Power supply pin (+3.3 V)
140
CLVS
O
Control signal output to selection the spindle control filter constant at CLVS.
141
VSS
—
Ground pin
142
MDSOUT
O
Frequency error output pin of internal CLV circuit.
143
VDD
—
Power supply pin (+3.3 V)
144
MDPOUT
O
Phase error output pin of internal CLV circuit.
145
DFCT
I
Not used. (Connected to ground.)
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from CD decoder, digital servo
processor IC.
147
EXCK
O
Subcode serial data reading clock signal output to CD decoder, digital servo processor
IC.
148
SBIN
I
Subcode serial data input from CD decoder, digital servo processor IC.
149
VSS
—
Ground pin
150
SCOR
I
Subcode sync (S0+S1) detection signal input from CD decoder, digital servo
processor IC.
151
WFCK
I
Write frame clock signal input from CD decoder, digital servo processor IC.
152
VDD5V
—
Power supply pin (+5 V)
153
XRCI
I
Not used. (Fixed at L.)
154
VDDS
—
Power supply pin (+5 V)
155
C2PO
I
C2 pointer signal input from CD decoder, digital servo processor IC.
156
VDD
—
Power supply pin (+3.3 V)
157
DBCK
O
Not used. (Open)
158
BCLK
I
Bit clock signal (2.8224 MHz) input from CD decoder, digital servo processor IC.
159
DDAT
O
Not used. (Open)
160
MDAT
I
Signal data input from CD decoder, digital servo processor IC.
161
VSS
—
Ground pin
162
DLRC
O
Not used. (Open)
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from CD decoder, digital servo processor
IC.
164
XRST
I
Reset signal input from mechanism control IC. (L: reset)
165
IFS0
I
Not used. (Connected to ground.)
166
IFS1
I
Not used. (Connected to VDD.)
167
XTAL
I
33.8688 MHz clock signal input from clock generator IC.
168
VSS
—
Ground pin
169
XTL2
O
33.8688 MHz clock signal output to clock generator IC.
170
XTL1
I
33.8688 MHz clock signal input from clock generator IC.
171
VDD
—
Power supply pin (+3.3 V)
172 to 176
D0 to D4
I/O
Two-way data bus signal input from/output to mechanism control IC.
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