DOWNLOAD Sony CDX-M850MP Service Manual ↓ Size: 6 MB | Pages: 59 in PDF or view online for FREE

Model
CDX-M850MP
Pages
59
Size
6 MB
Type
PDF
Document
Service Manual
Brand
Device
Car Audio
File
cdx-m850mp.pdf
Date

Sony CDX-M850MP Service Manual ▷ View online

21
CDX-M850MP
• IC303  M30626FHPGP-054 (SYSTEM CONTROL) (MAIN Board (2/2))
Pin No.
Pin Name
I/O
Pin Description
1
SIRCS
I
Remote control data input
2
FP CTRL
O
Front panel open/close speed control signal
3
CD SO/TSO
O
CD servo serial data output
4
CD SI/TSI
I
CD servo serial data input     Not used. (Open)
5
CD CKO/TCKO
O
CD servo serial clock output     Not used. (Open)
6
BYTE
I
L fixed terminal
7
CNVSS
I
Flash write-in signal input
8
XIN
I
Sub clock signal input (32kHz)
9
XOUT
O
Sub clock signal output (32kHz)
10
RESET
I
CPU reset signal input
11
OSC OUT
O
Main clock signal output (6MHz)
12
VSS
Ground
13
OSC IN
I
Main clock signal input (6MHz)
14
VCC1
Power supply pin (+5V)
15
NMI
I
Non maskable interrupt signal input
16
CD PACK
I
CD text pack synchronized signal input
17
DAVN
I
RDS data acquisition detect signal
18
BU IN
I
Back-up power detect signal
19
NS MASK
O
Noise mask signal output
20
BEEP
O
Beep signal output
21
FLW IN
I
OSC frequency shift signal for DC/DC conv.     Not used. (Open)
22
NCO
O
Not used. (Open)
23
SA CLK
O
Spectrum analyzer clock signal output
24
TEL ATT
I
telephone mute detect signal input
25
ATT
O
Mute signal output
26
VOL ATT
O
Electronic volume mute signal output
27
I2C CKO
O
Tuner/E-volume BUS clock output
28
I2C SIO
O
Tuner/E-volume BUS data output
29
UNI SO
O
SONY BUS data output
30
UNI SI
I
SONY BUS data input
31
UNI CKO
O
SONY BUS clock output
32
TUNER ATT
O
Tuner attenuate signal output
33
EESIO
I/O
EEPROM data input/output
34
EECKO
O
EEPROM clock output
35
NCO
O
Not used. (Open)
36
ADSO1
O
Not used. (Open)
37
ADSO2
O
Not used. (Open)
38
NCO
O
Not used. (Open)
39
HOLD
I
Flash write-in signal input
40
AMP DIAG
I
Amplifier diagnosis signal input
41
AMP STB
O
Amplifier strobe signal output
42
AMP ON
O
Not used. (Open)
43
TUNER ON
O
Not used. (Open)
44
WRI/WR
I
Flash write-in signal input
45
CD LIMIT
I
CD limit detect signal input     Not used. (Open)
46
CD D SW
I
CD disc SW detect signal input     Not used. (Open)
47
CD PH1
I
CD PH1 detect signal input
48
CD INSW/PH2
I
CD IN SW/PH2 detect signal input     Not used. (Open)
49
PH3
I
CD PH3 detect signal input     Not used. (Open)
50
DST SEL1
I
Destination select signal input
51
DST SEL2
I
Destination select signal input     Not used. (Open)
52
CD LM LO
O
CD loading motor control signal output     Not used. (Open)
22
CDX-M850MP
Pin No.
Pin Name
I/O
Pin Description
53
CD LM EJ
O
CD eject motor control signal output     Not used. (Open)
54
CD RST
O
CD servo reset signal output
55
CD AO
O
CD servo command/parameter discri. output     Not used. (Open)
56
CD STB
O
CD servo data strobe signal output     Not used. (Open)
57
CD TSTB
O
CD servo text strobe signal output     Not used. (Open)
58
CD RFOK
I
CD servo RFOK signal input
59
CD XTALEN
O
CD servo crystal OSC control signal output     Not used. (Open)
60
VCC2
Power supply pin (+5V)
61
RESET OUT
O
Display CPU reset signal output
62
VSS
Ground
63
TEST IN
I
Test mode setting detect signal input
64
BUS ON
O
BUS ON control signal output
65
SYS RST
O
System reset signal output
66
BUS/AUX
O
BUS/AUX select control signal output
67
LINK OFF
O
Link OFF control signal output
68
ACC IN
I
Accessory key ON detect signal input
69
ILL IN
I
Ilumination line detect signal input
70
RC IN1
I
Rotary commander signal input 1
71
NCO
O
Not used. (Open)
72
CD SELF SW
I
CD self SW detect signal input
73
TU ATT IN
I
Tuner mute control signal input
74
CLOSE SW
I
Front panel close detect signal input
75
OPEN SW
I
Front panel open detect signal input
76
I-DET
I
Front panel current detect signal input
77
MOT–
O
Front panel open/close control signal output
78
MOT+
O
Front panel open/close control signal output
79
ROMC EN
I
ROM correction enable signal input
80
QUALITY
I
Tuner noise detect signal input
81
MPTH
I
Tuner multi-path signal input
82
VSM
I
S-meter signal input
83
SA IN
I
SA data input
84
KEY IN1
I
Key signal input 1
85
KEY IN0
I
Key signal input 0
86
RC IN0
I
Rotary commander signal input 0
87
KEY ACK2
I
Key acknowledge detect signal input 2
88
KEY ACK0
I
Key acknowledge detect signal input 0
89
KEY ACK1
I
Key acknowledge detect signal input 1
90
OPEN KEY
I
Open key detect signal input
91
RAM BU
I
RAM reset detect signal input
92
FLD ON
O
FL driver power supply ON/OFF signal output
93
FL ON
O
FL power supply ON/OFF signal
94
AVSS
Ground
95
DISP CE
O
Display CPU chip enable output
96
VREF
A/D converter reference voltage (+5V)
97
AVCC
Power supply pin (+5V)
98
DISP SI/RX
I
Display CPU BUS data input
99
DISP SO/TX
O
Display CPU BUS data output
100
DISP CKO
O
Display CPU BUS clock output
23
23
CDX-M850MP
• IC2  M30833FJGP-073 (DISPLAY SYSTEM CONTROL) (DISPLAY Board)
Pin No.
Pin Name
I/O
Pin Description
1
SYS CE
I
Main chip enable input
2
NC
I
Not used. (Open)
3
FL DAT3
O
FL serial data output
4
NC
O
Not used. (Open)
5
FL CLK IN
I
FL serial clock input
6
BYTE
I
L fixed terminal
7
CNVSS
I
Flash write-in signal input
8
NC
O
Not used. (Open)
9
NC
O
Not used. (Open)
10
RESET
I
CPU reset signal input
11
XOUT
O
Main clock signal output (30MHz)
12
VSS
Ground
13
XIN
I
Main clock signal input (30MHz)
14
VCC
Power supply pin (+5V)
15
NMI
I
Non maskable interrupt signal input
16
NC
O
Not used. (Open)
17
NC
O
Connecting to pin 20.
18
NC
O
Not used. (Open)
19
NC
O
Not used. (Open)
20
NC
O
Connecting to pin 17.
21
LAT
O
FL data LAT output
22
BK
O
FL BK output
23
GCP2
O
FL GCP2 outpit
24
NC
O
Not used. (Open)
25
GCP1
O
FL GCP1 output
26
NC
O
Not used. (Open)
27
GCP4
O
FL GCP4 output
28
GCP3
O
FL GCP3 output
29
SYS SO
O
Main BUS data output
30
SYS SI
I
CPU BUS data input
31
SYS CLK
O
Main BUS clock input
32
NC
O
Not used. (Open)
33
FL DAT1
O
FL serial data output
34
NC
O
Not used. (Open)
35
FL CLK
O
FL serial clock output
36
LCD CE
O
LCD driver chip enble output
37
LCD INH
O
LCD driver inhibit output
38
NC
O
Not used. (Open)
39
HOLD
I
Flash write-in signal input
40 – 43
NC
O
Not used. (Open)
44
WRI/WR
I
Flash write-in signal input
45 – 59
NC
O
Not used. (Open)
60
VCC
O
Power supply pin (+5V)
61
NC
O
Not used. (Open)
62
VSS
O
Ground
63 – 93
NC
O
Not used. (Open)
94
AVSS
Ground
95
NC
O
Not used. (Open)
96
VREF
Power supply pin (+5V)
97
AVCC
Power supply pin (+5V)
98
RXD1
Not used. (Open)
99
FL DAT2
O
FL serial data output
100
FL CLK IN
I
FL serial clock input
24
24
CDX-M850MP
• R-ch is omitted due to
  same as L-ch.
• Signal path
            :CD
            :CD-R/RW(MP3)
84
85
82
83
16
12
D/A
CONV
TRACKING
ERROR
FORCUS
ERROR
9
1
OSC
EFM
DEMOD
SERVO
CTL
RF
EQ
52
56
54
55
DSUB CODE
PROCESS
8
7
6
5
4
3
2
33
40
9
10
83
84
85
35
36
37
28
I/F
87
86
97
98
LD
DRIVE
Q1
FOCUS
COIL
DRIVE
TRACKING
COIL
DRIVE
SLED
MOTOR
DRIVE
SPINDLE
MOTOR
DRIVE
LOADING
MOTOR
DRIVE
6
5
23
2
15
16
17
18
13
14
11
12
9
10
26
62 63 64 65
17
18
59
M902
(SLED)
M901
(SPINDLE)
M903
(LOADING)
SW3
(DISC IN)
 SW2
(SELF)
  SW4
(LIMIT)
X1
16.9344MHz
X2
12.288MHz
OPTICAL PICK-UP
KSS-721A
I-V
CONV.
CDL
STB
AO
TSO
38 PACK
34 TSTB
TSI
27 FLAG
TSCK
CD_RST
RFOK
XTALEN
/RESET
STANDBY
REQ
MIDIO(I2C_SDA)
MICK(I2C_SCL)
X1
SDO
SDIO
BCKIA
LRCKIA
63 XTAL
65 EXTAL
INSW/PH2
11
SW5
(DOWN)
D_SW
SELF SW
LIMIT_SW
LOAD
EJECT
R-CH
TUNER
SECTION
A
A-ATT
TUNER
SECTION
B
23
24
M
M
M
LOUT
ROUT
PACK
TSTB
TSI
TSCK
SI
RFOK
FLAG
C16M
DIN
DECXRST
DECSTBY
DECINT
SDA
SCL
DOUT
SCKIN
SCKO
LRCKIN
LRCK
SO
SCK
STB
AO
XTALEN
RST
RSTX
92
BUCHK
91
BUSON
78
UNI CK
77
UNI_SI
76
UNI_SO
75
LINKOFF
BU CHK
BUSON
BUS-CLK
BUS-SI
BUS-SO
LINK-OFF
93
A-ATT
A
C
B
D
E
F
PD
LD
B
D
A
C
E
F
PD
A+5V
LD
APC
FCS-
FCS+
TRK+
TRK-
SL-
SL+
SP+
SP-
LD-
LD+
FOCUS
COIL
TRACKING
COIL
FD
TD
SD
MD
LOAD
EJECT
IC3
CD MASTER CONTROL
IC1
RF AMP,DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC2
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING MOTOR DRIVE
FD
TD
SD
MD
38
28
29
30
31
32
33
34
62
9
12
13
14
2
3
72
80
1
19
39
5
81
6
4
1
2
IC12
IC5
DSP
IC7
5V    3.3V
17
3
14
12
7
16
18
6
8
13
4
2
5
15
9
11
SYSRST
DISPLY
SECTION
C
DISPLY
SECTION
D
71
CDMON
CDMON
94
CDON
CDON
73
CLOSE
CLOSE
74
OPEN
OPEN
21-23
25-29
20-13
3,2,31
1,12,4
11,7,10
46,47
49-51
53-55
3,4
7,10
11,15
38-36
34-31
41,42
45,44
32
30
5
16
17
43
OE
CS1
OE
CE
WR
WR
IO0-IO7
DQ1-DQ3,
IO4-IO8
AD0-AD16
A0-A16
IC4
S-RAM
+2.5V
(IC5)
BU+3.3V
3
+2.5V
REG
2
IC6
4-2. BLOCK DIAGRAM — CD SECTION —
(Page 25)
(Page 25)
(Page 26)
(Page 26)
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