Sony ZS-M30 Service Manual ▷ View online
29
ZS-M30
58
JOG–A
I
Jog controller (A) input
59
KEY–AD4
I
Key input terminal
60
KEY–AD3
I
Key input terminal
61
KEY–AD2
I
Key input terminal
62
COM3.3V–SHORT
I
COM3.3V voltage detection terminal
63
LED–SURROUND
—
Not used (OPEN)
64
CD–POWER
O
Power supply ON/OFF signal output for CD servo system
65
CD–C2P0
—
Not used (OPEN)
66
CD–SPH
O
CD High speed recording control signal output
67
CD–AGC CONT
O
CD AGC signal output
68
CD–SCLK
O
Subcode Q data transfer clock signal output for CD DSP IC (IC702)
69
MD–SRXD
I
UART communication data input from the MD mechanism controller (IC601)
70
MD–STXD
O
UART communication data output to the MD mechanism controller (IC601)
71
—
Not used (OPEN)
72
—
Not used (OPEN)
73
CD–CLK
O
Serial data transfer clock signal output to the CD DSP IC (IC702)
74
CD–XLAT
O
Serial data latch pulse signal output to the CD DSP IC (IC702)
75
CD–DATA
O
Serial data output to the CD DSP IC (IC702)
76
CD–XRST
O
CD reset signal output to the CD RF AMP (IC701),CD DSP IC (IC702)
77
CD SENSE
I
Internal status (SENSE) input from the CD DSP IC (IC702)
78
CD–SCOR
I
Subcode sync (SO +S1) detection signal input from the CD DSP IC (IC702)
79
CD–SQSO
I
Subcode Q data input from the CD DSP IC (IC702)
80
CD–RFH
O
CD RF level select output
81
CD–SQCK
O
Subcode Q data reading clock signal output to the CD DSP IC (IC702)
82,83
—
Not used (OPEN)
84
CD–DOOR
I
CD door open/close signal input
85
RMC
I
Remote control signal input
86
TEX
I
Sub system clock input terminal (32.768KHz)
87
TX
O
Sub system clock output terminal (32.768KHz)
88
VSS
—
Ground terminal
89
VDD
—
Power supply terminal (3.3V)
90-92
—
Not used (OPEN)
93
B/L–CONT
O
LCD backlight control signal output
94
ACCHK
I
AC power supply voltage detection terminal
95
P–COM
O
Power ON/OFF control signal output
96
—
Not used (OPEN)
97
TU–CE
O
PLL serial chip enable signal output to the tuner IC (IC1)
98
TU–DATA
O
PLL serial data output to the tuner IC (IC1)
99
TU–CLK
O
PLL serial data transfer clock signal output to the tuner IC (IC1)
100
TU–COUNT
I
PLL serial data input from the tuner IC (IC1)
Pin No.
Pin name
I/O
Description
30
ZS-M30
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+ 1.65 V) generation output terminal
4 – 9
A – F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input terminal for setting laser power
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor
15
TEMPR
O
Output terminal for a temperature sensor reference voltage
16
SWDT
I
Writing serial data input from the CXD2654R (IC504)
17
SCLK
I
Serial data transfer clock signal input from the CXD2654R (IC504)
18
XLAT
I
Serial data latch pulse signal input from the CXD2654R (IC504)
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ)
inputfrom the CXD2654R (IC504)
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I/O
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I/O
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I/O
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2654R (IC504)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2654R (IC504)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2654R (IC504)
33
AUX
O
Auxiliary signal (I3 signal/temperature signal) output to the CXD2654R (IC504)
34
FE
O
Focus error signal output to the CXD2654R (IC504)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2654R (IC504)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD264R (IC504)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2654R (IC504)
38
RF
O
Playback EFM RF signal output to the CXD2654R (IC504)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I/O
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
• MD BOARD IC502 CXA2523AR (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Pin Description
31
ZS-M30
• MD BOARD IC 504 CXD2654R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
1
MNT0 (FOK)
O
Focus OK signal output to the MD mechanism controller (IC601)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller (IC601)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller (IC601)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC601)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC601)
6
SCLK
I (S) Serial data transfer clock signal input from the MD mechanism controller (IC601)
7
XLAT
I (S) Serial data latch pulse signal input from the MD mechanism controller (IC601)
8
SRDT
O (3) Reading serial data signal output to the MD mechanism controller (IC601)
9
SENS
O (3) Internal status (SENSE) output to the MD mechanism controller (IC601)
10
XRST
I (S) Reset signal input from the MD mechanism controller (IC601) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC601)
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism
controller(IC601) “L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the MD mechanism controller (IC601)“L”:
playback mode, “H”: recording mode
14
XINT
O
Interrupt status output to the MD mechanism controller (IC601)
15
TX
I
Recording data output enable signal input from the MD mechanism controller(IC601)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512 Fs = 45.1584 MHz) input terminal
17
OSCO
O
System clock signal (512 Fs = 45.1584 MHz) output terminal
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode (for digital optical input) Not
used
20
DIN1
I
Digital audio signal input terminal when recording mode (for digital optical input)
21
DOUT
O
Digital audio signal output terminal when playback mode (for digital optical output)
Not used
22
DATAI
I
Serial data input terminal Not used (fixed at “L”)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “L”)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “L”)
25
ADDT
I
Recording data input from the A/D, D/A converter (IC604)
26
DADI
I
Playback data input from the A/D, D/A converter (IC604)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC604)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC604)
29
FS256
O
Clock signal (11.2896 MHz) output terminal
30
DVDD
—
Power supply terminal (+3.3 V) (digital system)
31 – 34
A03
O
A00 O Address signal output to the D-RAM (IC505)
35
A10
O
Address signal output to the external D-RAM Not used (open)
36 – 40
A04 – A08
O
Address signal output to the D-RAM (IC505)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC505) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC505) “L” active
45
A09
O
Address signal output to the D-RAM (IC505)
Pin No.
Pin Name
I/O
Pin Description
32
ZS-M30
46
XRAS
O
Row address strobe signal output to the D-RAM (IC505) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC505) “L” active
48
D1
I/O
49
D0
I/O
Two-way data bus with the D-RAM (IC505)
50
D2
I/O
51
D3
I/O
52
MVCI
I (S) Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A) Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3 V) (analog system)
56
BIAS
I (A) Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A) Playback EFM RF signal input from the CXA2523AR (IC502)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3) Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A) Filter input for master clock of the recording/playback master PLL
61
FILO
O (A) Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A) Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A) Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC502)
64
BOTM
I (A) Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC502)
65
ABCD
I (A) Light amount signal (ABCD) input form the CXA2523AR (IC502)
66
FE
I (A) Focus error signal input from the CXA2523AR (IC502)
67
AUX1
I (A) Auxiliary signal (I3 signal/temperature signal) input from the CXA2523AR (IC502)
68
VC
I (A) Middle point voltage (+1.65 V) input from the CXA2523AR (IC502)
69
ADIO
O (A) Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3 V) (analog system)
71
ADRT
I (A) A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A) A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A) Sled error signal input from the CXA2523AR (IC502)
75
TE
I (A) Tracking error signal input from the CXA2523AR (IC502)
76
DCHG
I (A) Connected to the +3.3 V power supply
77
APC
I (A) Error signal input for the laser automatic power control Not used (fixed at “H”)
78
ADFG
I (S) ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC502)
79
F0CNT
O
Filter f0 control signal output to the CXA2523AR (IC502)
80
XLRF
O
Serial data latch pulse signal output to the CXA2523AR (IC502)
81
CKRF
O
Serial data transfer clock signal output to the CXA2523AR (IC502)
82
DTRF
O
Writing serial data output to the CXA2523AR (IC502)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic
powercontrol
84
TESTO
—
Not used (OPEN)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC501)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC501)
87
DVDD
—
Power supply terminal (+3.3 V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC501)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC501)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
Pin No.
Pin Name
I/O
Pin Description
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