Sony TA-F501ES Service Manual ▷ View online
45
TA-F501ES
MAIN BOARD IC1800 MB89F538L-F501-X101 (SUB SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Pin Description
1
I-LIMIT
I
Abnormal current detection signal input from the digital power amplifier
2
MOD2
—
Not used (Pull down)
3
REG-TEMP
I
Thermistor connection terminal for abnormal temperature detection Not used
4 to 9
CUR1 to CUR6
I
Current detection terminal for speaker output section
Not used (Connected to ground)
10
CUR7/D-AMP-
I
Abnormal temperature detection terminal for the power amplifier Not used
TEMP-AD
11
AVCC
—
Power supply (+3.3V)
12
AVR
I
Reference voltage (+3.3V) input terminal
13
AVSS
—
Ground
14
U-MAIN
I
Clock signal input from main system controller
15
AC-OFF
I
AC off detection signal input terminal “L”: AC off
16
PWM-MODE
I
PWM mode setting terminal Normally: fixed at “H”
17, 18
DC1, DC2
I
DC offset detection signal input terminal Not used
19
RST
I
System reset signal input from the main system controller “L”: reset
20, 21
MOD0, MOD1
I
Setting terminal for memory access mode
22
X0
I
System clock input terminal (12.5 MHz)
23
X1
O
System clock output terminal (12.5 MHz)
24
VSS
—
Ground
25
VOL-CLK
O
Serial data transfer clock signal output to the power amplifier power supply
control D/A converter
26
VOL-DATA
O
Serial data output to the power amplifier power supply control D/A converter
27
VOL-LAT
O
Serial data latch pulse signal output to the power amplifier power supply control
D/A converter
28
DAC-MUTE
O
Muting on/off control signal output to the power amplifier power supply control
circuit
29, 30
(P23), (P22)
—
Not used
31
4/8SW
I
IMPEDANCE SELECTOR switch input terminal Not used
32
SUR (A) RY
O
Relay drive signal (for surround speaker) output terminal Not used (Open)
33
SUR (B) RY
O
Relay drive signal (for surround speaker) output terminal Not used (Open)
34
4/8OUT
I
Relay drive signal (for selection) output terminal Not used (Open)
35
HIC-TEMP
I
Over temperature detection signal input from the digital power amplifier
36
EN
O
Enable/Disable control signal output to the digital power amplifier
37
DC3
I
DC offset detection signal input terminal Not used
38
INIT
O
System reset signal output to the stream processor
39
DC4
I
DC offset detection signal input terminal Not used
40
(P10)
—
Not used
41
SOFT-MUTE
O
Muting on/off control signal output to the stream processor
42
U-SUB1
I
Serial data input from main system controller
43
LAT4
O
Serial data latch pulse signal (for surround back) output terminal Not used
44
LAT3
O
Serial data latch pulse signal (for surround) output terminal Not used
45
LAT2
O
Serial data latch pulse signal (for center) output terminal Not used
46
LAT1
O
Serial data latch pulse signal (for front) output to the stream processor
47
FRONT (A) RY
O
Relay drive signal (for front speaker A) output terminal Not used (Open)
48
FRONT (B) RY
O
Relay drive signal (for front speaker B) output terminal Not used (Open)
49
NC
—
Not used (Open)
50
DC5
I
DC offset detection signal input terminal Not used
51
SHIFT
O
Serial data transfer clock signal output to the stream processor
52
SCDT
O
Serial data output to the stream processor
46
TA-F501ES
53
DC6
I
DC offset detection signal input terminal Not used
54
DC7
I
DC offset detection signal input terminal Not used
55
SUR-BACK-RY
O
Relay drive signal (for surround back speaker) output terminal Not used (Open)
56
VCC
—
Power supply (+3.3V)
57
SOFT-MUT (SB)
O
Muting on/off control signal (for surround back) output terminal Not used (Open)
58
MUTE
I
Muting on/off control signal input from the system controller
59
U-USB2
O
Serial data output to main system controller
60
INT21/SCK2
I
Clock signal input terminal for memory access
61
INT22/SO2/SDA
O
Serial data output terminal for memory access
62
INT23/SI2/SCL
I
Serial data input terminal for memory access
63
ALL-CH-DC-PROTECT
I
DC offset detection signal input terminal
64
CENTER SP-RY
O
Relay drive signal (center) output terminal Not used (Open)
Pin No.
Pin Name
I/O
Pin Description
47
TA-F501ES
DSP BOARD IC2 ADSST-AVR-1115 (DSP)
Pin No.
Pin Name
I/O
Pin Description
1
VDDINT
—
Power supply (+1.2V)
2, 3
CLKCFG0, CLKCFG1
I
Clock frequency setting terminal
4, 5
BOOTCFG0,
I
Boot mode setting terminal for DSP
BOOTCFG1
6
GND
—
Ground
7
VDDEXT
—
Power supply (+3.3V)
8
GND
—
Ground
9
VDDINT
—
Power supply (+1.2V)
10
GND
—
Ground
11
VDDINT
—
Power supply (+1.2V)
12
GND
—
Ground
13
VDDINT
—
Power supply (+1.2V)
14
GND
—
Ground
15
INT_REQ
O
Interrupt status output to the main system controller
16
DIR_ERR
O
PLL lock error signal and data error flag output to the main system controller
17
AD7
I/O
Two-way data bus and address signal output with S-RAM
18
GND
—
Ground
19
VDDINT
—
Power supply (+1.2V)
20
GND
—
Ground
21
VDDEXT
—
Power supply (+3.3V)
22
GND
—
Ground
23
VDDINT
—
Power supply (+1.2V)
24 to 26
AD6 to AD4
I/O
Two-way data bus and address signal output with S-RAM
27
VDDINT
—
Power supply (+1.2V)
28
GND
—
Ground
29, 30
AD3, AD2
I/O
Two-way data bus and address signal output with S-RAM
31
VDDEXT
—
Power supply (+3.3V)
32
GND
—
Ground
33, 34
AD1, AD0
I/O
Two-way data bus and address signal output with S-RAM
35
XWR
O
Data write enable signal output to the S-RAM “L” active
36, 37
VDDINT
—
Power supply (+1.2V)
38
GND
—
Ground
39
XRD
O
Read strobe signal output to the S-RAM “L” active
40
ALE
O
Address latch enable signal output terminal
41 to 43
AD15 to AD13
I/O
Two-way data bus and address signal output with S-RAM
44
GND
—
Ground
45
VDDEXT
—
Power supply (+3.3V)
46
AD12
I/O
Two-way data bus and address signal output with S-RAM
47
VDDINT
—
Power supply (+1.2V)
48
GND
—
Ground
49 to 52
AD11 to AD8
I/O
Two-way data bus and address signal output with S-RAM
53
A16
O
Address signal output to S-RAM
54
VDDINT
—
Power supply (+1.2V)
55
GND
—
Ground
56, 57
A17, A18
O
Address signal output to S-RAM
58
GND
—
Ground
59
VDDEXT
—
Power supply (+3.3V)
60
VDDINT
—
Power supply (+1.2V)
61
GND
—
Ground
48
TA-F501ES
62
PF_CE
I/O
Chip enable signal input/output terminal Not used (Open)
63
SPI_MAS
O
Master/slave selection signal output terminal “L”: DSP is master
64
DPSOA
O
PCM audio signal output terminal
65
DPSOB
O
PCM audio signal output terminal Not used
66
VDDINT
—
Power supply (+1.2V)
67
GND
—
Ground
68
VDDINT
—
Power supply (+1.2V)
69
GND
—
Ground
70
DPSOC
O
PCM audio signal output terminal Not used
71
DPSOD
O
PCM audio signal output terminal Not used
72
VDDINT
—
Power supply (+1.2V)
73
VDDEXT
—
Power supply (+3.3V)
74
GND
—
Ground
75
VDDINT
—
Power supply (+1.2V)
76
GND
—
Ground
77
DPSOE
O
PCM audio signal output terminal Not used
78
DPSIA
I
PCM audio signal (digital input) input terminal
79
DPSIB
I
PCM audio signal input terminal from the A/D converter
80
DPSIC
I
PCM audio signal output terminal Not used
81
DPSID
I
PCM audio signal output terminal Not used
82
DPSIE
I
PCM audio signal output terminal Not used
83
VDDINT
—
Power supply (+1.2V)
84, 85
GND
—
Ground
86
DPDVLRCK
O
Sampling clock signal output terminal for PCM audio signal output
87
DPDVBCK
O
Bit clock signal output terminal for PCM audio signal output
88
DPLRCK
I
Sampling clock signal input terminal for PCM audio signal input
89
DPBCK
I
Bit clock signal input terminal for PCM audio signal input
90
VDDINT
—
Power supply (+1.2V)
91, 92
GND
—
Ground
93
VDDEXT
—
Power supply (+3.3V)
94
DPFSCK
I
Master clock signal input terminal
95
GND
—
Ground
96
VDDINT
—
Power supply (+1.2V)
97
XNONAUDIO
I
Digital input signal switch control signal input terminal
98
XSF_CE
O
Chip enable signal output to the flash memory
99
VDDINT
—
Power supply (+1.2V)
100
GND
—
Ground
101
VDDINT
—
Power supply (+1.2V)
102
GND
—
Ground
103
VDDINT
—
Power supply (+1.2V)
104
GND
—
Ground
105
VDDINT
—
Power supply (+1.2V)
106
GND
—
Ground
107, 108
VDDINT
—
Power supply (+1.2V)
109
GND
—
Ground
110
VDDINT
—
Power supply (+1.2V)
111
GND
—
Ground
112
VDDINT
—
Power supply (+1.2V)
113
GND
—
Ground
114
VDDINT
—
Power supply (+1.2V)
Pin No.
Pin Name
I/O
Pin Description
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