Sony STR-DB830 / STR-DB930 / STR-V929X Service Manual ▷ View online
— 50 —
Pin No.
91
92 – 94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117 – 120
I/O
—
O
O
I
I
O
I
O
—
—
—
—
I/O
I
I
I
O
O
—
—
I
I
I
I
I
Description
Ground
External RAM address output
Not used
Test data input “L” = normal “H” = test (Connecting to ground)
PLL input frequency select “L” = 256Fs “H” = 128Fs (Connecting to ground)
PLL output frequency select “L” = 768Fs “H” = 1024Fs (Connecting to ground)
Master clock input
Master clock output (Not used)
Ground
+3.3V
Ground for PLL cell
VDD for PLL cell
PLL output/test clock input
PLL cell oscillation enable “L” oscillation enable “H” oscillation stop (Connecting to ground)
Test data input “L” = normal “H” = test (Connecting to ground)
Frequency counter input (Connecting to ground)
LRCK0 divider output
BCK0 divider output
Ground
+3.3V
BCK input
BCK input
LRCK input
LRCK input
Serial data input
Pin Name
V
SS
0
EA13 – EA15
EA16
TSTA
PLDIVF
PLDIVB
CLKI
CLKO
V
SS
1
V
DD
0
AV
SS
AV
DD
PLLCK
XPLLEN
TST
LRCT
LROUT
BKOUT
V
SS
2
V
DD
1
BCK0
BCK1
LRCK0
LRCK1
SIA – SID
— 51 —
IC1201
MB90573PFV-G-190-BND SYSTEM CONTROL(DIGITAL BOARD)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
Description
Pin Name
SCLK
SI
SO
CS
IC
D.SIG
5.1CH
VCC
SIN0
SOT0
N.C
N.C
XHDWR
XHDRD
SOD
XHDCS
HD7
HD6
HD5
HD4
HD3
HD2
HD1
HD0
HA0
XRST
HRDY
CS
CCLK
CDTI
CDTO
PD
VSS
C
96KHz
N.C
N.C
DVCC
DVSS
N.C
N.C
AVCC
AVR+
AVR-
AVSS
EVSTB
EVDATA
EVCLK
DISPMR
DISPDATA
O
I
O
O
O
I
O
—
I
O
O
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
I
O
—
—
O
I
I
—
—
O
—
—
—
—
—
O
O
O
I
I
To CXD9511Q clock
To CXD9511Q data input
To CXD9511Q data output
To CXD9511Q chip select
To CXD9511Q reset(Pull Down near CXD9511Q)
ZERO data detect
5.1CH muting.
Power supply +5 V
UART input. Used for rewriting flash memory
UART output. Used for rewriting flash memory
Not used (Connected to ground)
Not used (Connected to ground)
To CXD2712 data write
To CXD2712 data read
To CXD2712 LFE detection
To CXD2712 chip select
To CXD2712 HCIF data I/O
To CXD2712 HCIF data I/O
To CXD2712 HCIF data I/O
To CXD2712 HCIF data I/O
To CXD2712 HCIF data I/O
To CXD2712 HCIF data I/O
To CXD2712 HCIF data I/O
To CXD2712 HCIF data I/O
To CXD2712 address
To CXD2712 reset
To CXD2712 ready
To AK4526A chip select
To AK4526A clock
To AK4526A data input
To AK4526A data output
To AK4526A reset
Ground (Connected to ground)
External power regulator capacitor 0.1u is connected to this terminal.
To AK4526A Dfs
Not used (Connected to ground)
Not used (Connected to ground)
Digital power supply +5 V
Digital Ground (Connected to ground)
Not used (Connected to ground)
Not used (Connected to ground)
Analog power supply +5 V
Power supply +5 V
Ground (Connected to ground)
Ground (Connected to ground)
To TC9299 strobe
To TC9299 data
To TC9299 clock
Display master request (Connected to MCU U.MREQ)
Display data (Connected to MCU U.DATA)
Pin No.
— 52 —
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
Description
Pin Name
SLVDTA/REQ
DISPCLK
N.C
VCC
S.LAT
S.DATA
S.CLK
DATA IN
AUSTOP
STEREO
N.C
N.C
VSS
N.C
TH
PROTEC
STOP
N.C
N.C
N.C
N.C
VIDEO(SW4)
X1A
X0A
VIDEO(SW3)
VIDEO(SW2)
VIDEO(SW1)
DIGITAL 1/4
TAPE NO/ YES
VIDEO3 NO/ YES
DTS NO/ YES
ACMUTE
96K NO/YES
T.MUTE
S.MUTE
HSTX
MD2
MD1
MD0
REST
VSS
XO
XI
VCC
PO0
PO1
RY-4/B
RY-PRE
RY-FRONT/A
RY-FRONT/B
O
I
I
—
O
O
O
I
I
I
I
I
—
I
I
I
I
I
I
I
I
O
—
—
O
O
O
I
I
I
I
O
I
O
O
—
—
—
—
I
—
—
—
—
I
I
O
O
O
O
Slave data/request (Connected to MCU U.SREQ)
Display clock (Connected to MCU U.CLOCK)
Not used (Connected to ground)
Power supply +5 V
To tuner latch
To tuner data
To tuner clock
PLL data in
Auto stop input
Stereo input
Not used (Connected to ground)
Not used (Connected to ground)
Ground (Connected to ground)
Not used (Connected to ground)
TH Protector input
Protector input
AC power check
Not used (Connected to ground)
Not used (Connected to ground)
Not used (Connected to ground)
Not used (Connected to ground)
Video select SW4
Not used
Not used
Video select SW3
Video select SW2
Video select SW1
Digital function
Tape NO/YES input
I VIDEO3 NO/ YES input
DTS NO/ YES input
Power amp mute ON/OFF output
96K NO/YES input
Tuner muting
Surround muting (Connected to ground)
Hardware standby (Connected to power supply +5 V)
MD2 (To MCU MD2)
MD1 (Connect to power supply)
MD0 (To MCU MD0)
Reset (Connected to MB90553 U.RESET)
Ground (Connected to ground)
External ceramic filter 16MHz is connected to this terminal
External ceramic filter 16MHz is connected to this terminal
Power supply +5V
Flash memory rewrite (Connected to ground)
Flash memory rewrite (Connected to ground)
4/8 relay
Pre relay
Front speaker A relay
Front speaker B relay
Pin No.
— 53 —
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
I/O
Description
Pin Name
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
—
—
Center speaker relay
Rear speaker relay
Sub Woofer relay
Head phone relay
Power relay
Analog/digital selection
Digital input select B
Digital input select A
Direct pass relay
To LC89055 clock
To LC89055 latch
To LC89055 data
To LC89055 C-bit
Error output to LC89055
Non PCM sync detect flag LC89055
Non PCM data detect flag LC89056
C-bit change flag LC89055
Xtal status Frag LC89055
Ground (Connected to ground)
Not used (Connected to ground)
RY-CENTER
RY-REAR
RY-WOOFER
RY-HP
RY-POWER
ANG/DIG
DIG-INB
DIG-INA
XMODE
CL
CE
DI
DO
ERROR
BYSYNC
AUTO
CSFLAG
XSTATE
VSS
N.C
Pin No.
Click on the first or last page to see other STR-DB830 / STR-DB930 / STR-V929X service manuals if exist.