Sony SDP-E800 Service Manual ▷ View online
— 45 —
— 44 —
4-7. IC BLOCK DIAGRAMS
• MAIN SECTION
ATT
FIR1
IIR
FIR2
FIR3
L.I.P
(X8)
(X8)
PLM
PLM
3rd order
NOISE SHAPER
AC, DC
DITHER
CLOCK
GENERATOR
ATT
FIR1
IIR
FIR2
FIR3
L.I.P
(X8)
(X8)
V
SS
2
R1(+)
V
SS
R1(–)
V
DD
V
DD
2
VSUB(C)R
DV
SS
R
DV
DD
R
DFV
DD
1
SPLM
20/16
XSEL
SYSM
ATT
SHIFT
LATCH
INIT
BCKI
LRCKI
DATAI
VSUB(D)R
DFV
SS
VSUB(D)L
INAF
512F
S
O
256F
S
O
128F
S
O
INVI
INVO1
MUTER
3rd order
NOISE SHAPER
MODE
“O” DETECT
MUTE
CIRCUIT
63
64
62
61
3 4
TIMING
CIRCUIT
S/P
9
10
11
12
13
14
15
16 17 18 19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
43
45
46
47
48
49
51
INVO2
50
52
53
54
55
56
57
58
59
60
MUTEL
TEST1
TEST2
DFV
DD
2
DV
DD
L
DV
SS
L
VSUB(C)L
V
DD
2
V
DD
V
SS
V
SS
2
1
V
SS
2
2
L2(+)
V
SS
L2(–)
5
V
DD
6
V
DD
2
7
VSUB(A)L
8
XV
DD
XOUT
XIN
XV
SS
XV
SS
VSUB(A)R
V
DD2
V
DD
R2(–)
V
SS
R2(+)
V
SS2
L1(–)
L1(+)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D3
D2
D1
D0
Y
W
S
C
D4
D5
D6
D7
A
B
D3
D2
D1
D0
Y
XY
OE
GND
V
CC
D4
D5
D6
D7
A
B
C
IC108 TC74HC157AF
IC106 TC74HC151AF
SELECT 11
1
1A
2
3
4
5
6
7
INPUT
INPUT
OUTPUT
OUTPUT
1A
1B
1Y
2A
2B
2Y
1B
1Y
2A
2B
2Y
GND 8
V
CC
STROBE
16
4A
15
14
13
11
12
11
10
INPUT
INPUT
OUTPUT
OUTPUT
G
4B
4Y
3A
4A
4B
4Y
3A
3B
9
3B
3Y
3Y
S
IC109 TC74HCU04AF
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
GND
IC115 TC74HC393AF
IC203 CXD8681M-TP
VREF- 2
VCOML 3
AINL+ 4
VOLTAGE
REFERENCE
DELTA-SIGMA
MODULATOR
DECIMATOR
CONTROLLER
VOLTAGE
REFERENCE
DECIMATION
FILTER
CALIBRATION
SRAM
SERIAL OUTPUT
INTERFACE
DELTA-SIGMA
MODULATOR
VREF+ 1
AINL- 5
ZCAL 6
VD 7
DGND 8
CAL 9
RST 10
SMODE 2 11
SMODE 1 12
LRCK 13
SCLK 14
VREF-
27
VCOMR
26
AINR+
25
VREF+
AINR-
24
VA
23
AGND
22
BGND
21
TEST
20
SEL24
19
CMODE
18
MCLK
17
FSYNC
16
SDATA
15
28
IC301, 1301, 2301 CXD8505BQ
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Q
A
Q
B
Q
C
Q
D
A
CLEAR
VCC
Q
A
Q
B
Q
C
Q
D
A
CLEAR
GND
— 46 —
IC305, 1305, 2305 LC7535M
NC 1
L 5dB IN 2
LCT 1 3
LCT 2 4
L 5dB OUT 5
NC 6
L 1dB IN 7
L 1dB OUT 8
LVM 9
VEE 10
NC 11
S 12
V
DD
13
V
SS
14
NC 15
R 5dB OUT
26
NC
30
R 5dB IN
29
RCT 1
28
RCT 2
27
NC
25
R 1dB IN
24
R 1dB OUT
23
RVM
22
V
CC
21
NC
20
CE
19
DI
18
CL
17
NC
16
LATCH
LEVEL SHIFT
CONTROL
SHIFT REGISTER
C
D
IC501 NJM2279M-TE2
IC701 TC5081AP
1
2
3
4
5
6
7
8
9
PHASE
COMPARATOR
AOUT
AIN
PDOUT
PHASE OUT
VDD
N. C.
S
R
GND
SW 1 2
VIN 2 3
VIN 3 1
MUTE 2 4
VOUT 2 5
GND 2 6
GND 1 7
SW 2
13
VIN 1
12
V-
14
MUTE 1
11
VOUT 1
10
NC
9
V+
8
1
2
— 47 —
• DISPLAY SECTION
IC602 TD62C950RF
Q
D
ST
ST
Q
D
CK
D
Q
Q
D
CK
24
25
23
22
21
26
27
28
36
40
39
38
37
39
38
37
35
34
33
32
31
1
20
29
60
41
30
OUT1
OUT20
H V
CC
P GND
L GND
CL
NC
STB
NC
NC
NC
S IN
V
DD
OUT40
OUT21
H V
CC
P GND
L GND
NC
CHG
NC
CK
NC
S OUT
V
DD
IC603 MSC1164GS-K
20 BIT
SHIFT
REGISTER
20 BIT
LATCH
GATE
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
32 31 30
29
28
27
26 25 24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC
NC
DOUT
LS
CL
V
CC
HVO20
HVO19
HVO18
HVO17
HVO16
HVO15
HVO14
HVO13
HVO12
HVO11
HVO1
Vhv
GND
CLK
DIN
CHG
NC
D
CK
CK
Q
HVO2
HVO3
HVO4
HVO5
HVO6
HVO7
HVO8
HVO9
HVO10
IC604 BA6208
1
2
3
4
5
6
7
8
9
NC
OUTPUT 2
Vcc
GND
NC
INPUT 2
INPUT 1
NC
MOTOR
DRIVE
MOTOR
DRIVE
REG
SWITCH
SWITCH
OUTPUT1
— 48 —
Function
DIN1
DIN2
E/DOUT
V
DD
R
VIN
VCO
GND
CKSEL
XMODE
AVOCK
TST1
TST2
SCLK
XLAT
SWDT
SRDT
DQSY
CKOUT
FS128
BCK
LRCK
DATAO
EROR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
I
O
–
I
I
O
–
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
Function
Pin No.
Pin Name
I/O
Data input with built-in amplifier (Responding to the coaxial optical module)
Data input (Responding to the optical module)
Emphasis, input bi-phase, validity flag output
Power supply (+5V)
VCO gain control input (Fixed at “H”)
VCO freerunning frequency setting input
LPF setting of PLL (Fixed at “L”)
Ground
System clock select input (384fs, 512fs) (Connected to the power supply.)
Reset input
Clock input for preventing PLL lock failure
Test input (Normally “L”)
Microcomputer IF clock input
Microcomputer IF latch/chip enable input
Microcomputer IF write data input
Microcomputer IF read data output
Microcomputer IF Sub-Q sync and ID sync output (Not used)
VCO clock output (Freerunning, 384fs, 512fs) (Not used)
128fs clock output (Not used)
Bit clock output
L/R clock output
Audio data output
PLL lock error mute output
4-10. IC PIN FUNCTIONS
• IC107 Digital Audio Interface Receiver (CXD8521M)
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