Sony SCD-XB780 Service Manual ▷ View online
57
SCD-XB780
Pin No.
Pin Name
I/O
Description
123
WCK
I
Operation clock signal input for PSP physical disc mark detection from the SACD decoder
124, 125
WAVDD
—
A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)
126
WARFI
I
Analog RF signal input for PSP physical disc mark detection from the SACD/CD RF amplifier
127
WAVRB
I
A/D bottom reference terminal for PSP physical disc mark detection
128, 129
WAVSS
—
A/D ground terminal (for PSP physical disc mark detection)
130
VSIO
—
Ground terminal (for I/O)
131 to 134
DQ7 to DQ4
I/O
Two-way data bus with the D-RAM
135
VDIO
—
Power supply terminal (+3.3V) (for I/O)
136 to 139
DQ3 to DQ0
I/O
Two-way data bus with the D-RAM
140
VSIO
—
Ground terminal (for I/O)
141
DCLK
O
Clock signal output to the D-RAM
142
DCKE
O
Clock enable signal output to the D-RAM
143
XWE
O
Write enable signal output to the D-RAM
144
XCAS
O
Column address strobe signal output to the D-RAM
145
XRAS
O
Row address strobe signal output to the D-RAM
146
VDIO
—
Power supply terminal (+3.3V) (for I/O)
147
TESTO
O
Output terminal for the test (normally: open)
148, 149
A11, A10
O
Address signal output to the D-RAM
150
VSC
—
Ground terminal (for core)
151, 152
A9, A8
O
Address signal output to the D-RAM
153
VDC
—
Power supply terminal (+2.5V) (for core)
154 to 157
A7 to A4
O
Address signal output to the D-RAM
158
VSIO
—
Ground terminal (for I/O)
159 to 162
A3 to A0
O
Address signal output to the D-RAM
163
VDIO
—
Power supply terminal (+3.3V) (for I/O)
164
XSRQ
O
Serial data request signal output to the SACD decoder
165
XSHD
I
Header flag signal input from the SACD decoder
166
SDCK
I
Serial data transfer clock signal input from the SACD decoder
167
XSAK
I
Serial data effect flag signal input from the SACD decoder
168
SDEF
I
Error flag signal input from the SACD decoder
169 to 176
SD0 to SD7
I
Stream data signal input from the SACD decoder
58
SCD-XB780
•
MAIN BOARD IC901 CXP973064-221R (CPU)
Pin No.
Pin Name
I/O
Description
1
MUT LOAD
O
Muting on/off control signal output to the loading motor drive “H”: muting on
2
AMUTE
O
Analog muting control signal output terminal Not used
3
DOCTRL
O
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
4
MUT 2D
O
Muting on/off control signal output to the focus/tracking coil drive “H”: muting on
5
MODE DAC
I
Not used
6
SP ON
O
Muting on/off control signal output to the spindle motor drive “H”: muting on
7
FCS JMP1
O
Focus jump 1 signal output
8
FCS JMP2
O
Focus jump 2 signal output
9
SENS CD
I
Internal status (SENSE) signal input from the digital signal processor
10
—
O
Not used
11
XCS IO
O
Chip select signal output to the programmable logic device
12
XCS DVD
O
Chip select signal output to the SACD decoder
13
VSS
—
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the SACD decoder and programmable logic device
22
INT0 DVD
I
Interrupt signal input from the SACD decoder
23
INT1 DVD
I
Interrupt signal input from the SACD decoder
24
T SENS
I
Input terminal of disc tray status detection signal from table sensor Not used
25
MIRR RF
I
Mirror signal input from the digital signal processor
26
SCOR CD
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
27
RDY DSD
I
Ready signal input from the DSD decoder “L”: ready
28
A1IN
I
Input terminal of sircs remote control signal from CONTROL A1 II Not used
29
COUT CD
I
Numbers of track counted signal input from the digital signal processor
30
IN SW
I
Loading in switch input terminal “L”: loading in
31
OUT SW
I
Loading out switch input terminal “L”: loading out
32
—
O
Not used
33
SQSO CD
I
Subcode Q data input from the digital signal processor
34
DATA CD
O
Serial data output to the digital signal processor
35
CLOK CD
O
Serial data transfer clock signal output to the digital signal processor
36
XLAT CD
O
Serial data latch pulse signal output to the digital signal processor
37
SQCK CD
O
Subcode Q data reading clock signal output to the digital signal processor
38
XRST
I
System reset signal input “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39
VSS
—
Ground terminal (digital system)
40
XTAL I
System clock input terminal (20 MHz)
41
EXTAL O
System clock output terminal (20 MHz)
42
VDD
—
Power supply terminal (+3.3V) (digital system)
43
SPDA
O
Spindle motor control signal output
44
APDO
O
Output terminal for offset adjustment of APEO (<z/. pin of SACD decoder)
45
LOAD IN
O
Loading motor drive signal (loading in direction) output
46
LOAD OUT
O
Loading motor drive signal (loading out direction) output
47
XLAT DSD
O
Serial data latch pulse signal output to the DSD decoder
48
SIN DSD
I
Serial data input from the DSD decoder
49
SOUT DSD
O
Serial data output to the DSD decoder and digital filter
50
SCK DSD
O
Serial data transfer clock signal output to the DSD decoder and digital filter
51
MUTE DSD
O
Muting on/off control signal output to the DSD decoder “H”: muting on
52
XDIS IO
O
Reset signal output to the programmable logic device “L”: reset
59
SCD-XB780
Pin No.
Pin Name
I/O
Description
53
FLOUT
O
Serial data output to the fluorescent indicator tube driver
54
FLCLK
O
Serial data transfer clock signal output to the fluorescent indicator tube driver
55
VSS
—
Ground terminal (digital system)
56
FLCS
O
Chip select signal output to the fluorescent indicator tube driver
57
LED DRV
O
LED drive signal output of the multi-channel indicator “H”: LED on
58
GFS DVD
I
Guard frame sync signal input from the SACD decoder
59
SP ERR
I
Spindle motor backward voltage input terminal
60 to 62
KEY0 to KEY2
I
Key input terminal (A/D input)
63
KEY3
I
Key input terminal (A/D input) Not used
64
JITTER
I
Jitter signal input
65
TE
I
Tracking error signal input from the SACD/CD RF amplifier
66
PI
I
Pull in signal input from the SACD/CD RF amplifier
67
FE
I
Focus error signal input from the SACD/CD RF amplifier
68
AVSS
—
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage input terminal (for A/D converter)
70
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
71
GFS CD
I
Guard frame sync signal input from the digital signal processor
72
SCLK CD
O
SENSE serial data reading clock signal output to the digital signal processor
73
MUTE CD
O
Muting on/off control signal output to the digital signal processor “H”: muting on
74
FOK CD
I
Focus OK signal input from the digital signal processor
75
LOCK CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
—
O
Not used
77
CLK RF
O
Serial data transfer clock signal output to the SACD/CD RF amplifier
78
EEPSIO
I/O
Two-way data bus with the EEPROM
79
EEPSCL
O
Clock signal output to the EEPROM
80
RXD
I
Not used
81
TXD
O
Not used
82
RM
I
Remote control signal input
83
DATA RF
I/O
Two-way data bus with the SACD/CD RF amplifier
84
XWR
O
Write strobe signal output to the SACD decoder and programmable logic device
85
XRD
O
Read strobe signal output to the SACD decoder and programmable logic device
86
NC
—
Not used
87
VDD
—
Power supply terminal (+3.3V) (digital system)
88
VSS
—
Ground terminal (digital system)
89
A0
O
Address signal output to the SACD decoder and programmable logic device
90 to 96
A1 to A7
O
Address signal output to the SACD decoder
97
INIT DF
O
Reset signal output to the digital filter “L”: reset
98
LATCH DF
O
Serial data latch pulse signal output to the digital filter
99
A1OUT
O
Output terminal of sircs remote control signal from CONTROL A1 II Not used
100
LD ON
O
Laser diode on/off control signal output to the SACD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
60
SCD-XB780
•
MAIN BOARD IC904 ISPLSI2032VE-110LT44-SA (PROGRAMMABLE LOGIC DEVICE)
Pin No.
Pin Name
I/O
Description
1
TRKSW
O
Tracking coil drive on/off control signal output “H”: drive on
2
ZEROL
I
L-ch zero data flag detection signal input from the digital filter
3
FS64
O
Clock signal (2.8224 MHz) output to the digital filter and DSD decoder
4
FS128
O
Clock signal (5.6448 MHz) output to the DSD decoder
5
YO
I
Clock signal (11.2896 MHz) input from the digital filter
6
VCC
—
Power supply terminal (+5V) (digital system)
7
XBSCAN
—
Not used
8
TDI
—
Not used
9
XCS
I
Chip select signal input from the CPU
10
XRD
I
Read strobe signal input from the CPU
11
XWR
I
Write strobe signal input from the CPU
12 to 16
D0 to D4
I/O
Two-way data bus with the SACD decoder and the CPU
17
GND
—
Ground terminal (digital system)
18
TDO
—
Not used
19 to 21
D5 to D7
I/O
Two-way data bus with the SACD decoder and the CPU
22
A
I
Address signal input from the CPU
23
CDPDSW
O
Photo diode for CD on/off control signal output “L”: photo diode on
24
RST
I
Reset signal input from the CPU “L”: reset
25
RST DSD
O
Reset signal output to the DSD decoder “L”: reset
26
RST DP
O
Reset signal output to the fluorescent indicator tube driver “L”: reset
27
TCK
—
Not used
28
VCC
—
Power supply terminal (+5V) (digital system)
29
XRESET
—
Not used
30
TMS
—
Not used
31
RST DVD
O
Reset signal output to the SACD decoder “L”: reset
32
RST CD
O
Reset signal output to the digital signal processor “L”: reset
33
DVDPDSW
O
Photo diode for SACD on/off control signal output “L”: photo diode on
34
MULTI
O
Multi/2ch selection signal output “L”: 2ch, “H”: multi
35
SDEN
O
Serial data enable signal output to SACD/CD RF amplifier
36
ISBTEST
O
Output terminal for disc inspection mode to DSD decoder
37
RMUTE
O
Front R-ch muting on/off control signal output “L”: muting on
38
LMUTE
O
Front L-ch muting on/off control signal output “L”: muting on
39
GND
—
Ground terminal (digital system)
40
GOE
—
Not used
41
ZEROR
I
R-ch zero data flag detection signal input from the digital filter
42
ZEROL
I
Front L-ch zero data flag detection signal input from the DSD decoder
43
ZEROR
I
Front R-ch zero data flag detection signal input from the DSD decoder
44
LIM SW
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
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