Sony SCD-XB780 Service Manual ▷ View online
53
SCD-XB780
Pin No.
Pin Name
I/O
Description
120
VCOR1
—
VCO oscillating range setting resistor connected terminal
121
VCOIN
I
VCO input terminal
122, 123 GNDA4, GNDA3
—
Ground terminal (analog system)
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input terminal
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
128, 129 VCCA3, VCCA2
—
Power supply terminal (+3.3V) (analog system)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134 GNDA2, GNDA1
—
Ground terminal (analog system)
135
SPO
O
Spindle motor control signal output
136
VC2
I
Middle point voltage (+1.65V) input terminal
137
MDIN2
I
Spindle motor servo drive signal input
138
MDIN1
I
MDP input terminal
139
VCCA1
—
Power supply terminal (+3.3V) (analog system)
140
CLVS
O
Control signal output for selection the spindle control filter constant at CLVS
141
VSS
—
Ground terminal (digital system)
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
—
Power supply terminal (+3.3V) (digital system)
144
MDPOUT
O
Phase error output terminal of internal CLV circuit
145
DEFECT
I
Defect signal input terminal Not used
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the digital signal processor
147
EXCK
O
Subcode serial data reading clock signal output to the digital signal processor
148
SBIN
I
Subcode serial data input from the digital signal processor
149
VSS
—
Ground terminal (digital system)
150
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
151
WFCK
I
Write frame clock signal input from the digital signal processor
152
VDD5V
—
Power supply terminal (+5V)
153
XRCI
I
RAM overflow signal input terminal Not used
154
VDDS
—
Power supply terminal (+5V) (digital system)
155
C2PO
I
C2 pointer signal input from the digital signal processor
156
VDD
—
Power supply terminal (+3.3V) (digital system)
157
DBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used
158
BCLK
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
159
DDAT
O
PCM data output terminal Not used
160
MDAT
I
Serial data input from the digital signal processor
161
VSS
—
Ground terminal (digital system)
162
DLRC
O
L/R sampling clock signal (44.1 kHz) output terminal Not used
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
164
XRST
I
Reset signal input from the programmable logic device “L”: reset
165
IFS0
I
Interface selection signal input terminal Fixed at “L” in this set
166
IFS1
I
Interface selection signal input terminal Fixed at “H” in this set
167
XTAL
I
33.8688 MHz clock signal input terminal
168
VSS
—
Ground terminal (digital system)
169
XTA2
O
System clock output terminal (33.8688 MHz)
170
XTA1
I
System clock input terminal (33.8688 MHz)
54
SCD-XB780
Pin No.
Pin Name
I/O
Description
171
VDD
—
Power supply terminal (+3.3V) (digital system)
172 to 176
D0 to D4
I/O
Two-way data bus with the CPU and programmable logic device
55
SCD-XB780
•
MAIN BOARD IC801 CXD2753R (DSD DECODER)
Pin No.
Pin Name
I/O
Description
1
VSC
—
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the CPU
3
MSCK
I
Serial data transfer clock signal input from the CPU
4
MSDATI
I
Serial data input from the CPU
5
VDC
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the CPU
7
MSREADY
O
Ready signal output to the CPU “L”: ready
8
XMSDOE
O
Serial data output enable signal output terminal Not used
9
XRST
I
Reset signal input from the programmable logic device “L”: reset
10
SMUTE
I
Soft muting on/off control signal input from the CPU “H”: muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input
12
VSIO
—
Ground terminal (for I/O)
13
EXCKO1
O
External clock 1 signal output terminal Not used
14
EXCKO2
O
External clock 2 signal output terminal Not used
15
LRCK
O
L/R sampling clock signal (44.1kHz) output terminal Not used
16
FRAME
O
Frame signal output terminal Not used
17
VDIO
—
Power supply terminal (+3.3V) (for I/O)
18 to 21
MNT0 to MNT3
O
Monitor signal output terminal Not used
22 to 25
TESTO
O
Output terminal for the test (normally: open)
26
TCK
I
Clock signal input terminal for the test (normally: fixed at “L”)
27
TDI
I
Input terminal for the test (normally: open)
28
VSC
—
Ground terminal (for core)
29
TDO
O
Output terminal for the test (normally: open)
30
TMS
I
Input terminal for the test (normally: open)
31
TRST
I
Reset terminal for the test (normally: fixed at “L”)
32 to 34 TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDC
—
Power supply terminal (+2.5V) (for core)
36
TESTO
O
Output terminal for the test (normally: open)
37
XBIT
O
Monitor terminal relative to DST Not used
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal Not used
42
VSIO
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used
45
VDIO
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used
48
XSUPAK
O
Supplementary data acknowledge signal output terminal Not used
49
VSC
—
Ground terminal (for core)
50
TESTO
O
Output terminal for the test (normally: open)
51, 52
TESTI
I
Input terminal for the test (normally: fixed at “L”)
53
TESTO
O
Output terminal for the test (normally: open)
54
VDC
—
Power supply terminal (+2.5V) (for core)
55
DSADML
O
DSD data output terminal for L-ch down mix Not used
56
DSADMR
O
DSD data output terminal for R-ch down mix Not used
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output
“L”: input (slave), “H”: output (master) Fixed at “L” in this set
“L”: input (slave), “H”: output (master) Fixed at “L” in this set
58
VSDSD
—
Ground terminal (for DSD data output)
59
BCKAI
I
Clock signal (5.6448 MHz) input from the programmable logic device
56
SCD-XB780
Pin No.
Pin Name
I/O
Description
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output Not used
61
PHREFI
I
Clock signal (2.8224 MHz) input from the programmable logic device
62
PHREFO
O
Phase reference signal output terminal for DSD output phase modulation Not used
63
ZDFL
O
Front L-ch Zero data flag detection signal output to the programmable logic device
64
DSAL
O
Front L-ch DSD data output to the digital filter
65
ZDFR
O
Front R-ch Zero data flag detection signal output to the programmable logic device
66
DSAR
O
Front R-ch DSD data output to the digital filter
67
VDDSD
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output terminal Not used
69
DSAC
O
Center DSD data output to the digital filter
70
ZDFLFE
O
Sub woofer zero data flag detection signal output terminal Not used
71
DSASW
O
Sub woofer DSD data output to the digital filter
72
VSDSD
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Surround L-ch zero data flag detection signal output terminal Not used
74
DSALS
O
Surround L-ch DSD data output to the digital filter
75
ZDFRS
O
Surround R-ch zero data flag detection signal output terminal Not used
76
DSARS
O
Surround R-ch DSD data output to the digital filter
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
O
Data output terminal for IEEE 1394 link chip interface Not used
80
VSC
—
Ground terminal (for core)
81, 82
IOUT2, IOUT3
O
Data output terminal for IEEE 1394 link chip interface Not used
83
VDC
—
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
O
Data output terminal for IEEE 1394 link chip interface Not used
86
VSIO
—
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal for IEEE 1394 link chip interface Not used
88
IFULL
I
Data transmission hold request signal input terminal for IEEE 1394 link chip interface Not used
89
IEMPTY
I
High speed transmission request signal input terminal for IEEE 1394 link chip interface
Not used
Not used
90
VDIO
—
Power supply terminal (+3.3V) (for I/O)
91
IFRM
O
Frame reference signal output terminal for IEEE 1394 link chip interface Not used
92
IOUTE
O
Enable signal output terminal for IEEE 1394 link chip interface Not used
93
IBCK
O
Data transmission clock signal output terminal for IEEE 1394 link chip interface Not used
94
VSC
—
Ground terminal (for core)
95
TESTI
I
Input terminal for the test (normally: fixed at “H”)
96
TESTI
I
Input terminal for the test (normally: fixed at “L”)
97
TESTI
I
Input terminal for the test (normally: fixed at “H”)
98
TESTO
O
Output terminal for the test (normally: open)
99
VDC
—
Power supply terminal (+2.5V) (for core)
100 to 105
TESTI
I
Input terminal for the test (normally: fixed at “L”)
106
VSIO
—
Ground terminal (for I/O)
107 to 109
TESTI
I
Input terminal for the test (normally: fixed at “L”)
110
VDIO
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
TESTI
I
Input terminal for disc inspection mode from the programmable logic device
116
VSC
—
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection Not used
121
VDC
—
Power supply terminal (+2.5V) (for core)
122
TESTI
I
Input terminal for the test (normally: fixed at “L”)
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