Sony SCD-XB780 Service Manual ▷ View online
49
SCD-XB780
•
MAIN BOARD IC509 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
DVDD0
—
Power supply terminal (+3.3V) (digital system)
2
XRST
I
Reset signal input from the programmable logic device “L”: reset
3
MUTE
I
Muting on/off control signal input from the CPU “H”: muting on
4
DATA
I
Serial data input from the CPU
5
XLAT
I
Serial data latch pulse signal input from the CPU
6
CLOK
I
Serial data transfer clock signal input from the CPU
7
SENS
O
Internal status (SENSE) signal output to the CPU
8
SCLK
I
SENSE serial data reading clock signal input from the CPU
9
ATSK
I/O
Input/output terminal for anti-shock Not used
10
WFCK
O
Write frame clock signal output to the SACD decoder
11
RFCK
O
RFCK signal output terminal Not used
12
XPCK
O
XPCK signal output terminal Not used
13
GFS
O
Guard frame sync signal output to the CPU
14
C2PO
O
C2 pointer signal output to the SACD decoder
15
SCOR
O
Subcode sync (S0+S1) detection signal output to the SACD decoder and CPU
16
C4M
O
4.2336 MHz clock signal output terminal Not used
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output to the SACD decoder
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output to the CPU
20
MIRR
O
Mirror signal output to the CPU
21
DFCT
I/O
Defect signal input/output terminal Not used
22
FOK
O
Focus OK signal output to the CPU
23
PWMI
I
Spindle motor external control signal input terminal Not used
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
25
MDP
O
Spindle motor servo drive signal output to the SACD decoder
26
SSTP
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used
28
DVDD1
—
Power supply terminal (+3.3V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output
30
SRDR
O
Sled servo drive PWM signal (–) output
31
TFDR
O
Tracking servo drive PWM signal (+) output
32
TRDR
O
Tracking servo drive PWM signal (–) output
33
FFDR
O
Focus servo drive PWM signal (+) output
34
FRDR
O
Focus servo drive PWM signal (–) output
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test
37
TES1
I
Input terminal for the test
38
VC
I
Middle point voltage (+1.65V) input terminal
39
FE
I
Focus error signal input from the SACD/CD RF amplifier
40
SE
I
Sled error signal input from the SACD/CD RF amplifier
41
TE
I
Tracking error signal input from the SACD/CD RF amplifier
42
CE
I
Middle point servo analog signal input
43
RFDC
I
RF signal input from the SACD/CD RF amplifier
44
ADIO
O
Output terminal for the test Not used
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
5-23.
IC PIN FUNCTION DESCRIPTION
50
SCD-XB780
Pin No.
Pin Name
I/O
Description
47
AVDD0
—
Power supply terminal (+3.3V) (analog system)
48
ASYO
O
EFM full-swing output terminal
49
ASYI
I
Asymmetry comparator voltage input terminal
50
RFAC
I
EFM signal input from the SACD/CD RF amplifier
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input terminal
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge pump output for master PLL
56
AVDD1
—
Power supply terminal (+3.3V) (analog system)
57
BIAS
I
Asymmetry circuit constant current input terminal
58
VCTL
I
VCO control voltage input terminal for the wideband EFM PLL Not used
59
V16M
O
VCO oscillation output terminal for the wideband EFM PLL Not used
60
VPCO
O
Charge pump output terminal for the wideband EFM PLL Not used
61
DVDD2
—
Power supply terminal (+3.3V) (digital system)
62
ASYE
I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on Not used
63
MD2
I
Digital out on/off control signal input from the CPU
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
64
DOUT
O
Digital audio signal output
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the SACD decoder and digital filter
66
PCMD
O
Serial data output to the SACD decoder and digital filter
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the SACD decoder and digital filter
68
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used
“H” is output when playback disc is emphasis on Not used
69
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “H” in this set
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “H” in this set
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.8688 MHz)
72
XTAO
O
System clock output terminal (33.8688 MHz) Not used
73
SOUT
O
Serial data output terminal Not used
74
SOCK
O
Serial data reading clock signal output terminal Not used
75
XOLT
O
Serial data latch pulse signal output terminal Not used
76
SQSO
O
Subcode Q data output to the CPU
77
SQCK
I
Subcode Q data reading clock signal input from the CPU
78
SCSY
I
Input terminal for resynchronism of guard subcode sync (S0+S1) Not used
79
SBSO
O
Subcode serial data output to the SACD decoder
80
EXCK
I
Subcode serial data reading clock signal input to the SACD decoder
51
SCD-XB780
•
MAIN BOARD IC701 CXD1882R-1 (SACD DECODER)
Pin No.
Pin Name
I/O
Description
1, 2
D5, D6
I/O
Two-way data bus with the CPU and programmable logic device
3
VSS
—
Ground terminal (digital system)
4
D7
I/O
Two-way data bus with the CPU and programmable logic device
5
A0
I
Address signal input from the CPU
6
VDD
—
Power supply terminal (+3.3V) (digital system)
7
A1
I
Address signal input from the CPU
8
VDD5V
—
Power supply terminal (+5V)
9 to 14
A2 to A7
I
Address signal input from the CPU
15
VSS
—
Ground terminal (digital system)
16
XWAIT
O
Wait signal output terminal Not used
17
XRD
I
Read strobe signal input from the CPU
18
XWR
I
Write strobe signal input from the CPU
19
XCS
I
Chip select signal input from the CPU
20, 21
XINT0, XINT1
O
Interrupt signal output to the CPU
22
VDD
—
Power supply terminal (+3.3V) (digital system)
23
XHRS
I
Not used
24
HDB7
O
Stream data signal output to the DSD decoder
25
VSS
—
Ground terminal (digital system)
26
HDB8
O
Error flag signal output to the DSD decoder
27
HDB6
O
Stream data signal output to the DSD decoder
28
VDDS
—
Power supply terminal (+5V) (digital system)
29
HDB9
O
Not used
30
HDB5
O
Stream data signal output to the DSD decoder
31
HDBA
O
Not used
32
HDB4
O
Stream data signal output to the DSD decoder
33
VSS
—
Ground terminal (digital system)
34
HDBB
O
Not used
35
HDB3
O
Stream data signal output to the DSD decoder
36
VDD
—
Power supply terminal (+3.3V) (digital system)
37
HDBC
O
Not used
38
VDDS
—
Power supply terminal (+5V) (digital system)
39
HDB2
O
Stream data signal output to the DSD decoder
40
HDBD
O
Not used
41
HDB1
O
Stream data signal output to the DSD decoder
42
VSS
—
Ground terminal (digital system)
43
HDBE
O
Not used
44
HDB0
O
Stream data signal output to the DSD decoder
45
HDBF
O
Not used
46
XSAK
O
Serial data effect flag signal output to the DSD decoder
47
VDDS
—
Power supply terminal (+5V) (digital system)
48
XDCK
O
Serial data transfer clock signal output to the DSD decoder
49
XSHD
O
Header flag signal output to the DSD decoder
50
VDD
—
Power supply terminal (+3.3V) (digital system)
51
REDY
O
Not used
52
VSS
—
Ground terminal (digital system)
53
XSRQ
I
Serial data request signal input from the DSD decoder
52
SCD-XB780
Pin No.
Pin Name
I/O
Description
54
HINT
O
Not used
55
XS16
O
Not used
56
HA1
I
Not used
57
XPDI
I/O
Not used
58
VDDS
—
Power supply terminal (+5V) (digital system)
59, 60
HA0, HA2
I
Not used
61
VSS
—
Ground terminal (digital system)
62, 63
HCS0, HCS1
I
Not used
64
VDD
—
Power supply terminal (+3.3V) (digital system)
65
DASP
I/O
Not used
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM
70
VSS
—
Ground terminal (digital system)
71
MDB4
I/O
Two-way data bus with the D-RAM
72
VDD5V
—
Power supply terminal (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM
76
XMWR
O
Write enable signal output to the D-RAM
77
VDD
—
Power supply terminal (+3.3V) (digital system)
78
XRAS
O
Row address strobe signal output to the D-RAM
79, 80
MA0, MA1
O
Address signal output to the D-RAM
81
VSS
—
Ground terminal (digital system)
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM
88
VDD
—
Power supply terminal (+3.3V) (digital system)
89
MA8
O
Address signal output to the D-RAM
90
VSS
—
Ground terminal (digital system)
91
MA9
O
Address signal output to the D-RAM
92
MA10/MNT1
O
RF data signal output terminal Not used
93
MA11/MNT2
O
Operation clock signal output for PSP physical disc mark detection to DSD decoder
94
XMOE
O
Output enable signal output to the D-RAM
95
XCAS
O
Column address strobe signal output to the D-RAM
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM
98
VSS
—
Ground terminal (digital system)
99
MDBA
I/O
Two-way data bus with the D-RAM
100
VDD
—
Power supply terminal (+3.3V) (digital system)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM
103
VDD5V
—
Power supply terminal (+5V)
104 to 106 MDBD to MDBF
I/O
Two-way data bus with the D-RAM
107
GFS
O
Guard frame sync signal output to the CPU
108
VSS
—
Ground terminal (digital system)
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply terminal (+3.3V) (digital system)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground terminal (analog system)
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal Not used
117
RFIN
I
RF signal input from the SACD/CD RF amplifier
118, 119 VCCA5, VCCA4
—
Power supply terminal (+3.3V) (analog system)
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