Sony SA-WSLF10 / SS-CTL10 / SS-TSL10 / SS-TSL11 Service Manual ▷ View online
37
SA-WSLF10/SS-CSL10/TSL10/TSL11
IC903
NJM2235V (TE2)
– VIDEO I/O Board –
IC902
MM1623BFBE
1
VCC1
2
C IN
3
MUTE 1
4
CVBS IN
28 VCC2
23 CVBS OUT
25 S1
150k
Ω
BIAS
12
CB IN
150k
Ω
BIAS
CLAMP
6dB
6dB
6
Y IN
7
GND
8
BIAS
CLAMP
BIAS
6dB
9
I/P
10
CY IN
11
CLP
13
MUTE2
5
YC MIX
+
6dB
–6dB
6dB
27 S-DC OUT
24 S2
LOW-PASS
FILTER
21 Y OUT
22 GND2
6.75MHz
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
75
Ω
DRIVER
20 CY OUT
75
Ω
DRIVER
S-DC OUT
S1/S2
26 C OUT
LOW-PASS
FILTER
6.75MHz
75
Ω
DRIVER
CLAMP
150k
Ω
BIAS
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
18 CB OUT
19 GND2
17 GND2
15 GND2
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
14
CR IN
150k
Ω
BIAS
16 CR OUT
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
6dB
6dB
1
2
3
4
6
5
7
8
VIN 1
SW 1
SW 2
V+
VIN 3
V OUT
GND
VIN 2
BIAS
BUFFER
OVER
CURRENT
PROTECTOR
LATCH
&
DRIVER
OVER HEAT
PROTECTOR
REGULATOR
+
–
–
+
–
–
RESET
VREF
COMPARATOR
ERROR AMP
OSC
1
VIN
2
SW OUT
3
GND
4
VOS
5
S.S
– 15V-REG Board –
IC800
SI-8150S
38
SA-WSLF10/SS-CTL10/TSL10/TSL11
MAIN BOARD IC525 CXD9702BQ (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XRST
I
Reset signal input from the system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input terminal Not used
5
VDDI
-
Power supply terminal (+2.6V)
6
BCKI3
I
Bit clock signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+2.6V)
11
VSS
-
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal "L": internal clock, "H": external clock
Fixed at "L" in this set
Fixed at "L" in this set
14
SCKOUT
O
Internal system clock output terminal Not used
15
LRCKI1
I
L/R sampling clock signal input from the A/D converter and digital audio interface receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the A/D converter and digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter and digital audio interface receiver
19
LRCKO
O
L/R sampling clock signal output to the stream processor and RF modulator
20
BCKO
O
Bit clock signal output to the stream processor and RF modulator
21
VSS
-
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23
SDO1
O
Audio serial data output to the stream processor
24
SDO2
O
Audio serial data output to the RF modulator
25
SDO3
O
Audio serial data output to the stream processor
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
S/PDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the A/D converter and digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the A/D converter and digital audio interface receiver
30
SDI2
I
Audio serial data input from the A/D converter
31
VSS
-
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write signal input terminal Not used
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
-
Power supply terminal (+2.6V)
41
VSS
-
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
•
IC Pin Function Description
39
SA-WSLF10/SS-CSL10/TSL10/TSL11
Pin No.
Pin Name
I/O
Description
46
VDDE
-
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at "H" in this set
48
VSS
-
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at "H" in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
-
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
TST1
O
Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal "L": enhanced mode, "H": normal mode
Fixed at "H" in this set
Fixed at "H" in this set
58
MOD0
I
Operation mode setting terminal "L": single chip mode, "H": can not use
Fixed at "L" in this set
Fixed at "L" in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
-
Power supply terminal (+2.6V)
61
VSS
-
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
Not used
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
-
Power supply terminal (+2.6V)
71
VSS
-
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
-
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
-
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
-
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
-
Power supply terminal (+2.6V)
101
VSS
-
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
-
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
-
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114
SDI3
I
Audio serial data input from the A/D converter
115
SDI4
I
Audio serial data input terminal Not used
40
SA-WSLF10/SS-CTL10/TSL10/TSL11
Pin No.
Pin Name
I/O
Description
116
SYNC
I
Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
117
TST2
I
Not used
118
GP11
I
Not used
119
TST3
I
Not used
120
VDDI
-
Power supply terminal (+2.6V)
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