Sony SA-WCT500 / SS-CT500 Service Manual ▷ View online
SA-WCT500/SS-CT500
77
MAIN BOARD IC4 ADSST-AVR-1115 (DSP)
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V) (for core)
2
CLKCFG0
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at “L” in this set
Fixed at “L” in this set
3
CLKCFG1
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at “H” in this set
Fixed at “H” in this set
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode selection signal input terminal Fixed at “H” in this set
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V) (for core)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V) (for core)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V) (for core)
14
GND
-
Ground terminal
15
INT_REQ
O
Interrupt request signal output to the system controller
16
DIR_ERR
I
Error signal input from the digital audio interface receiver “H”: error
17
AD7
I/O
Two-way address and data bus terminal Not used
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V) (for core)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V) (for core)
24 to 26
AD6 to AD4
I/O
Two-way address and data bus terminal Not used
27
VDDINT
-
Power supply terminal (+1.2V) (for core)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way address and data bus terminal Not used
31
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way address and data bus terminal Not used
35
WR*
O
Write enable signal output terminal Not used
36, 37
VDDINT
-
Power supply terminal (+1.2V) (for core)
38
GND
-
Ground terminal
39
RD*
O
Read enable signal output terminal Not used
40
ALE
O
Address latch enable signal output terminal Not used
41 to 43
AD15 to AD13
I/O
Two-way address and data bus terminal Not used
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
46
AD12
I/O
Two-way address and data bus terminal Not used
47
VDDINT
-
Power supply terminal (+1.2V) (for core)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way address and data bus terminal Not used
53
A16
-
Not used
54
VDDINT
-
Power supply terminal (+1.2V) (for core)
55
GND
-
Ground terminal
56, 57
A17, A18
-
Not used
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
60
VDDINT
-
Power supply terminal (+1.2V) (for core)
61
GND
-
Ground terminal
62
PF_CE
-
Not used
63
SPI_MAS
-
Not used
64
DPSOA
O
Audio signal output to the stream processor and S-AIR connector
65
DPSOB
O
Audio signal output to the S-AIR connector
66
VDDINT
-
Power supply terminal (+1.2V) (for core)
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V) (for core)
SA-WCT500/SS-CT500
78
Pin No.
Pin Name
I/O
Description
69
GND
-
Ground terminal
70
DPSOC
O
Audio signal output to the stream processor
71
DPSOD
O
Audio signal output terminal Not used
72
VDDINT
-
Power supply terminal (+1.2V) (for core)
73
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V) (for core)
76
GND
-
Ground terminal
77
DPSOE
O
Audio signal output to the HDMI transmitter and S-AIR connector
78
DPSIA
I
Audio signal input from the digital audio interface receiver
79
DPSIB
I
Audio signal input from the HDMI receiver, digital media port connector, AUDIO IN jack and
tuner (FM/AM)
tuner (FM/AM)
80 to 82
DPSIC to DPSIE
I
Audio signal input from the HDMI receiver
83
VDDINT
-
Power supply terminal (+1.2V) (for core)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the stream processor, HDMI transmitter and S-AIR con-
nector
nector
87
DPDVBCK
O
Bit clock signal output to the stream processor, HDMI transmitter and S-AIR connector
88
DPLRCK
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
89
DPBCK
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
90
VDDINT
-
Power supply terminal (+1.2V) (for core)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
94
DPFSCK
I
Master clock signal input from the digital audio interface receiver and HDMI receiver
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V) (for core)
97
NONAUDIO*
I
Audio data input from the digital audio interface receiver
98
SF_CE*
-
Not used
99
VDDINT
-
Power supply terminal (+1.2V) (for core)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V) (for core)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V) (for core)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V) (for core)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V) (for core)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V) (for core)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V) (for core)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V) (for core)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V) (for core)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V) (for core)
121
RESET*
I
Reset signal input from the system controller “L”: reset
122
SPIDS*
I
Device selection signal input from the system controller
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V) (for core)
125
SPICLK
I
Serial data transfer clock signal input from the system controller
126
MISO
O
Serial data output to the system controller
127
MOSI
I
Serial data input from the system controller
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V) (for core)
130
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
131
AVDD
-
Power supply terminal (+1.2V) (analog system)
SA-WCT500/SS-CT500
79
Pin No.
Pin Name
I/O
Description
132
AVSS
-
Ground terminal (analog system)
133
GND
-
Ground terminal
134
CLKOUT
O
Local clock signal output terminal Not used
135
EMU*
O
Emulation status signal output terminal Not used
136
TDO
O
Test data output terminal (for JTAG) Not used
137
TDI
I
Test data input terminal (for JTAG) Not used
138
TRST*
I
Test reset signal input terminal (for JTAG) Not used
139
TCK
I
Test clock signal input terminal (for JTAG) Not used
140
TMS
I
Test mode selection signal input terminal (for JTAG) Not used
141
GND
-
Ground terminal
142
CLKIN
I
System clock input terminal (25 MHz)
143
XTAL
O
System clock output terminal (25 MHz)
144
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
143
XTAL
O
System clock output terminal (25 MHz)
144
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
SA-WCT500/SS-CT500
80
MAIN BOARD IC1002 R5F3640MDFAR (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAMP_SCDT/
DIR_DIN
O
Serial data output to the digital audio interface receiver and stream processor
2
DAMP_SHIFT/
DIR_CLK
O
Serial data transfer clock signal output to the digital audio interface receiver and stream
processor
processor
3
XCEC_DI
I
CEC serial data input from the HDMI connector
4
SIRCS_IN
I
SIRCS signal input from the remote control receiver
5
DSP MOSI
O
Serial data output to the DSP
6
DSP MISO
I
Serial data input from the DSP
7
DSP_SPICLK
O
Serial data transfer clock signal output to the DSP
8
BYTE
I
External data bus width selection signal input terminal Fixed at “L” in this set
9
CNVss
I
Processor mode selection signal input terminal
10
ROM_SDA
I/O
Two-way data bus with the EEPROM
11
ROM_SCL
O
Serial data transfer clock signal output to the EEPROM
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to "H"
For several hundreds msec. after the power supply rises, “L” is input, then it change to "H"
13
Xout
O
System clock output terminal (5 MHz)
14
Vss
-
Ground terminal
15
Xin
I
System clock input terminal (5 MHz)
16
Vcc1
-
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt signal input terminal Not used
18
DIR_ZERO
I
Zero data detection signal input from the digital audio interface receiver
19
DIR_CSFLAG
I
Channel status fl ag input from the digital audio interface receiver
20
DRIVE_OCP(DIAG)
I
Shut down signal input from the power amplifi er “L”: shut down
21
FAN_CTRL
O
Fan motor control signal output terminal “L”: fan motor on
22
S-AIR_I2C_SCL
I/O
Two-way I2C clock bus with S-AIR connector
23
DMPORT_DET
I
Digital media port adapter connection detection signal input terminal
“L”: digital media port adapter is connected
“L”: digital media port adapter is connected
24
S-AIR_I2C_SDA
I/O
Two-way I2C data bus with S-AIR connector
25
A_SEL5
O
Audio selection signal output terminal
26
CEC_DO
O
CEC serial data output to the HDMI connector
27
DIR ERROR
I
Error signal input from the digital audio interface receiver “H”: error
28
A_SEL4
O
Audio selection signal output terminal
29
I2C_CLK
I/O
Two-way I2C clock bus terminal Not used
30
I2C_DATA
I/O
Two-way I2C data bus terminal Not used
31
DMPORT_TX_OUT
O
Serial data output to the digital media port connector
32
DMPORT_RX_IN
I
Serial data input from the digital media port connector
33, 34
A_SEL3, A_SEL2
O
Audio selection signal output terminal
35
VC_SEL0
O
Video selection signal output terminal
36
VC_SEL1
O
Video muting control signal output terminal
37
VIDEO_SEL0
O
Video selection signal output terminal
38
VIDEO_SEL1
O
Video muting control signal output terminal
39, 40
A_SEL1, A_SEL0
O
Audio selection signal output terminal
41
RDS_DATA
I
RDS serial data input from the TUNER (FM/AM) (AEP, Russian and UK models only)
42
ST_CE
O
Chip enable signal output to the tuner (FM/AM)
43
ST_DI
I
Serial data input from the tuner (FM/AM)
44
ST_CLK
O
Serial data transfer clock signal output to the tuner (FM/AM)
45
ST_DO
O
Serial data output to the tuner (FM/AM)
46
TUNED
I
Tuned detection signal input from the tuner (FM/AM) “L”: tuned
47
DIR_XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
48
DIR_RST
O
Reset signal output to the digital audio interface receiver “L”: reset
49
DIR_HCE
O
Chip enable signal output to the digital audio interface receiver
50
DSP_SPIDS
O
Device selection signal output to the DSP
51
DSP_RESET
O
Reset signal output to the DSP “L”: reset
52
PCM_MULTI
O
Input data selection signal output terminal
53
FL_DATA
O
Serial data output to the fl uorescent indicator tube
54
FL_CS
O
Chip select signal output to the fl uorescent indicator tube
55
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube
56
FL_RST
O
Reset signal output to the fl uorescent indicator tube “L”: reset
57
LED1
O
LED drive signal output terminal for POWER indicator “H”: LED on
Click on the first or last page to see other SA-WCT500 / SS-CT500 service manuals if exist.