Sony SA-WCT500 / SS-CT500 Service Manual ▷ View online
SA-WCT500/SS-CT500
73
Pin No.
Pin Name
I/O
Description
L1
IPCLK3
I
Clock signal input terminal Not used
L2
BVS
I
Vertical sync signal input terminal Not used
L3
BHS
I
Horizontal sync signal input terminal Not used
L4
IO_3.3V
-
Power supply terminal (+3.3V)
L10
D_GND
-
Ground terminal
L11
CORE_1.8V
-
Power supply terminal (+1.8V)
L12 to
L15
D_GND
-
Ground terminal
L16
CORE_1.8V
-
Power supply terminal (+1.8V)
L17
D_GND
-
Ground terminal
L23 to
L26
PD4 to PD7
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
M1
DIP_CLEAN_HS_
OUT
-
Not used
M2
DIP_EXT_CLAMP
-
Not used
M3
DIP_EXT_COAST
-
Not used
M4
IPCLK2
I
Clock signal input terminal Not used
M10 to
M17
D_GND
-
Ground terminal
M23
IO_3.3V
-
Power supply terminal (+3.3V)
M24,
M25
LVDS_GND
-
Ground terminal
M26
LVDS_3.3V
-
Power supply terminal (+3.3V)
N1
IPCLK0
I
Clock signal input terminal Not used
N2
DIP_RAW_HS_CS
-
Not used
N3
DIP_AODD
-
Not used
N4
DIP_BODD
-
Not used
N10 to
N17
D_GND
-
Ground terminal
N23 to
N26
PD0 to PD3
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
P1 to P3
ADATA2 to ADATA0
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
P4
IPCLK1
I
Output data clock signal input from the clock generator
P10 to
P17
D_GND
-
Ground terminal
P23
IO_3.3V
-
Power supply terminal (+3.3V)
P24
DCLK
O
Output data clock signal output to the clock generator
P25
DHS
O
Horizontal sync signal output to the HDMI transmitter
P26
DEN
O
Data enable signal output to the HDMI transmitter
R1 to R4
ADATA6 to ADATA3
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
R10 to
R17
D_GND
-
Ground terminal
R23
JTAG_BS_TDI
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
R24
JTAG_BS_RST
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
R25
JTAG_BS_TCK
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
R26
DVS
O
Vertical sync signal output to the HDMI transmitter
T1 to T4
ADATA10 to ADATA7
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
T10
D_GND
-
Ground terminal
T11
CORE_1.8V
-
Power supply terminal (+1.8V)
T12 to
T15
D_GND
-
Ground terminal
T16, T17
CORE_1.8V
-
Power supply terminal (+1.8V)
T23
IO_3.3V
-
Power supply terminal (+3.3V)
T24
JTAG_BS_TMS
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
T25
JTAG_BS_TDO
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
SA-WCT500/SS-CT500
74
Pin No.
Pin Name
I/O
Description
T26
GPIO_44
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
U1 to U4
ADATA14 to ADATA11
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
U10, U11
CORE_1.8V
-
Power supply terminal (+1.8V)
U12 to
U15
D_GND
-
Ground terminal
U16, U17
CORE_1.8V
-
Power supply terminal (+1.8V)
U23, U24
PWM1, PWM2
-
Not used
U25
PPWR
-
Not used
U26
PBIAS
-
Not used
V1 to V4
ADATA18 to ADATA15
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
V23
IO_3.3V
-
Power supply terminal (+3.3V)
V24
PWM0
-
Not used
V25
SLAVE_SDA
-
Not used
V26
SLAVE_SCL
-
Not used
W1 to
W4
ADATA22 to ADATA19
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
W23
OCM_INT1
-
Not used
W24
OCM_TIMER1
-
Not used
W25
OCM_UDI_0
-
Not used
W26
ODM_UDO_0
-
Not used
Y1
AVS
I
Vertical sync signal input from the HDMI receiver
Y2
AHS
I
Horizontal sync signal input from the HDMI receiver
Y3
AHREF_DE
I
Data enable signal input from the HDMI receiver
Y4
ADATA23
I/O
Digital video signal input from the HDMI receiver and digital video signal output to the HDMI
transmitter
transmitter
Y23
IO_3.3V
-
Power supply terminal (+3.3V)
Y24
OCM_INT2
-
Not used
Y25
VGA1_SDA
-
Not used
Y26
VGA1_SCL
-
Not used
AA1
NC
-
Not used
AA2 to
AA4
DGND_ADC
-
Ground terminal
AA23
MSTR0_SDA
I/O
Two-way data bus with the EEPROM
AA24
MSTR0_SCL
O
Serial data transfer clock signal output to the EEPROM
AA25
VGA0_SDA
-
Not used
AA26
VGA0_SCL
-
Not used
AB1
A1P
I
Component video signal (PR/CR) input from the COMPONENT VIDEO IN jack
AB2
SV1P
-
Not used
AB3
AGND_ADC
-
Ground terminal
AB4
ADC_1.8V
-
Power supply terminal (+1.8V)
AB23
IO_3.3V
-
Power supply terminal (+3.3V)
AB24
IRO
-
Not used
AB25
MSTR2_SDA
-
Not used
AB26
MSTR2_SCL
-
Not used
AC1
C1P
I
Component video signal (Y) input from the COMPONENT VIDEO IN jack
AC2
B1P
I
Component video signal (PB/CB) input from the COMPONENT VIDEO IN jack
AC3
AGND_ADC
-
Ground terminal
AC4,
AC5
ADC_1.8V
-
Power supply terminal (+1.8V)
AC6
AGND_ADC
-
Ground terminal
AC7
VOUT2
-
Not used
AC8
AGND_ADC
-
Ground terminal
AC9
LBADC_3.3V
-
Power supply terminal (+3.3V)
AC10
LBADC_IN4
-
Not used
AC11
LBADC_GND
-
Ground terminal
AC12
AVSIN_DATA
-
Not used
AC13
EXTOSD_HS
-
Not used
AC14
IO_3.3V
-
Power supply terminal (+3.3V)
SA-WCT500/SS-CT500
75
Pin No.
Pin Name
I/O
Description
AC15
OCMADDR18
O
Address signal output to the fl ash memory
AC16
IO_3.3V
-
Power supply terminal (+3.3V)
AC17
OCMADDR11
O
Address signal output to the fl ash memory
AC18
IO_3.3V
-
Power supply terminal (+3.3V)
AC19
OCMADDR4
O
Address signal output to the fl ash memory
AC20
IO_3.3V
-
Power supply terminal (+3.3V)
AC21
OCMDATA13
I/O
Two-way data bus with the fl ash memory
AC22
IO_3.3V
-
Power supply terminal (+3.3V)
AC23
OCMDATA6
I/O
Two-way data bus with the fl ash memory
AC24
OCM_CS2N
O
Chip select signal output terminal Not used
AC25
OCN_RE_N
O
Read enable signal output to the fl ash memory
AC26
OCN_WE_N
O
Write enable signal output to the fl ash memory
AD1
AN
-
Not used
AD2
AGND_ADC
-
Ground terminal
AD3 to
AD5
ADC1_3.3V
-
Power supply terminal (+3.3V)
AD6,
AD7
ADC2_3.3V
-
Power supply terminal (+3.3V)
AD8
AGND_ADC
-
Ground terminal
AD9
RESET
I
Reset signal input from the video system controller “L”: reset
AD10
LBADC_IN3
-
Not used
AD11
LBADC_RETURN
-
Not used
AD12
AVSIN_WORDSEL
-
Not used
AD13
EXTOSD_VS
-
Not used
AD14
AVSOUT_DATA
-
Not used
AD15 to
AD20
OCMADDR19,
OCMADDR15,
OCMADDR12,
OCMADDR15,
OCMADDR12,
OCMADDR8,
OCMADDR5,
OCMADDR5,
OCMADDR1
O
Address signal output to the fl ash memory
AD21 to
AD23
OCMDATA14,
OCMDATA10,
OCMDATA10,
OCMDATA7
I/O
Two-way data bus with the fl ash memory
AD24
ROM_CS_N
O
Chip enable signal output to the fl ash memory
AD25,
AD26
OCM_CS0N,
OCM_CS1N
O
Chip select signal output terminal Not used
AE1
SV2P
-
Not used
AE2
B2P
-
Not used
AE3
AGND_ADC
-
Ground terminal
AE4
SV3P
-
Not used
AE5
B3P
-
Not used
AE6
AGND_ADC
-
Ground terminal
AE7
SV4P
-
Not used
AE8
BN2
-
Not used
AE9
AGND_ADC
-
Ground terminal
AE10,
AE11
LBADC_IN2,
LBADC_IN6
Not used
AE12
AIP_RAW_VS
-
Not used
AE13
AVSOUT_SCL
-
Not used
AE14
AVSOUT_WORDSEL
-
Not used
AE15 to
AE20
OCMADDR20,
OCMADDR16,
OCMADDR13,
OCMADDR16,
OCMADDR13,
OCMADDR9,
OCMADDR6,
OCMADDR6,
OCMADDR2
O
Address signal output to the fl ash memory
AE21 to
AE26
OCMDATA15,
OCMDATA11,
OCMDATA8,
OCMDATA2 to
OCMDATA0
I/O
Two-way data bus with the fl ash memory
AF1
A2P
-
Not used
SA-WCT500/SS-CT500
76
Pin No.
Pin Name
I/O
Description
AF2
C2P
-
Not used
AF3
BN
-
Not used
AF4
A3P
I
Composite video signal input from the VIDEO IN jack
AF5
C3P
-
Not used
AF6
CN
-
Not used
AF7
AN2
-
Not used
AF8
CN2
-
Not used
AF9
SVN
-
Not used
AF10
LBADC_IN1
I
Wake-up signal input from the video system controller
AF11
LBADC_IN5
-
Not used
AF12
AIP_RAW_HS_CS
-
Not used
AF13
EXTOSD_CLK
-
Not used
AF14
AVSIN_SCL
-
Not used
AF15 to
AF20
OCMADDR21,
OCMADDR17,
OCMADDR14,
OCMADDR10,
OCMADDR17,
OCMADDR14,
OCMADDR10,
OCMADDR7,
OCMADDR3
O
Address signal output to the fl ash memory
AF21
OCMADDR0
O
Address signal output terminal Not used
AF22 to
AF26
OCMDATA12,
OCMDATA9,
OCMDATA5 to
OCMDATA3
I/O
Two-way data bus with the fl ash
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