Sony SA-SLRT5 / SA-SRRT5 Service Manual ▷ View online
SA-SLRT5/SRRT5
SA-SLRT5/SRRT5
25
25
4-9. SCHEMATIC DIAGRAM - MAIN Section (3/3) (SA-SRRT5) -
• See page 17 for Waveforms. • See page 26 for IC Block Diagrams.
15
3.2
4
3.2
4.1
11.8
3.3
3.3
3.2
4
22
8.6
2.6
3.1
22
4
3.2
4
0.9
4.7
3.5
1
C9109
1
C9108
SUB_22V
D_GND
P_CONT2
P_CONT1
WS3.3V
12V
UNSW4V
D3.3V
JL9103
JL9102
R9116
0
R9117
0
0
R9119
0
R9112
BD33HA5WEFJ-E2
IC9103
VO
1
VO_S
2
GND
3
NC_4
4
EN
5
NC_6
6
NC_7
7
VCC
8
1
C9112
1
C9113
1k
R9115
MM1839A33NRE
IC9104
CONT
1
GND
2
NC
3
VOUT
4
VIN
5
1
C9124
1
C9123
UNSW3.3V
0
R9118
0
R9109
PVDD22V
T_GND
1k
R9114
MM3411A33URE
IC9105
CE
1
GND
2
VOUT
3
VDD
4
0
R9120
WS_GND
0.1
C9153
FB9152
FB9151
JL9301
2.2uH
L9151
10uH
L9152
RT8295BLZSP
IC9151
BOOT
1
VIN
2
SW
3
GND
4
FB
5
COMP
6
EN
7
SS
8
3.3k
R9153
10k
R9152
100k
R9151
0.1
C9157
0.0022
C9154
22
C9156
22
C9155
10k
R9154
3.3k
R9155
FB9171
1k
R9175
1
C9171
10
C9172
PQ200WNA1ZVU
IC9171
VIN
1
VC
2
VO
3
VADJ
4
GND
5
33k
R9173
10k
R9171
2.2uH
L9171
2.2k
R9172
6.3V
C9115
220
6.3V
220
C9114
0
R9177
10
C9152
CL9101
CL9100
0
R9158
D3.3V
D_GND
REAR MAIN (R) BOARD (3/3)
IC9103
IC9105
IC9104
IC9151
IC9171
+3.3V REGULATOR
+3.3V REGULATOR
+3.3V REGULATOR
+12V REGULATOR
4
5
7
(R)
BOARD
8
(1/3)
9
>203S
10
REAR MAIN
11
(R)
BOARD
(2/3)
>204S
REAR MAIN
G
F
1
C
D
6
E
2
B
3
A
DC/DC CONVERTER
Note: IC9103 and IC9171 on the REAR MAIN (R) board cannot re-
place with single. When these parts are damaged, replace the
complete mounted board.
complete mounted board.
(Page 24)
(Page 23)
SA-SLRT5/SRRT5
SA-SLRT5/SRRT5
26
26
8
VCC
5
EN
6
N.C.
7
N.C.
+
–
–
OVER CURRENT
PROTECITON
THERMAL
SHUTDOWN
SOFT
START
2
VO_S
1
VO
3
GND
4
N.C.
IC8104 MM1839A33NRE (SA-SLRT5)
IC9104 MM1839A33NRE (SA-SRRT5)
IC9104 MM1839A33NRE (SA-SRRT5)
VOUT
4
CONT 1
GND 2
NC 3
VIN
5
+
–
VOLTAGE
REFERENCE
REGULATOR
CURRENT
LIMIT
THERMAL
SHUTDOWN
BIAS
IC8105 MM3411A33URE (SA-SLRT5)
IC9105 MM3411A33URE (SA-SRRT5)
IC9105 MM3411A33URE (SA-SRRT5)
VOUT
3
CE 1
GND 2
VDD
4
+
–
VOLTAGE
REFERENCE
CURRENT
LIMIT
BIAS
IC8151 RT8295BLZSP (SA-SLRT5)
IC9151 RT8295BLZSP (SA-SRRT5)
IC9151 RT8295BLZSP (SA-SRRT5)
BOOT
1
VIN
2
SW
3
GND
4
FB
5
COMP
6
EN
7
SS
8
S
R
Q
Q
–
+
FOLDBACK
CONTROL
SLOPE COMP
UV
COMPARATOR
CURRENT
COMPARATOR
CURRENT SENSE
AMPLIFIER
SHUTDOWN
COMPARATOR
LOCKOUT
COMPARATOR
OSCILLATOR
0.8V
+
+
–
VA
VCC
2.7V
1.2V
VA
VCC
EA
–
+
0.4V
INTERNAL
REGULATOR
–
+
–
+
+
–
I2C SERIAL
CONTROL
INTERFACE
CLOCK, PLL,
AND
SERIAL DATA
INTERFACE
PWM_HPM_L 1
PWM_HPP_L 2
PWM_HPM_R 3
PWM_HPP_R 4
PLL_FLTM 6
PLL_FLTP 7
LRCLK 22
SCLK 23
SDIN1 24
SDIN2 25
SDIN3 26
SDIN4 27
SDIN2 25
SDIN3 26
SDIN4 27
VR_DIG 28
RESET 16
HP_SEL 17
PDN 18
MUTE
ASEL_EMO2 10
EMO1 15
DVDD2_CORE 14
DVSS2_CORE 13
AVDD 9
VR_ANA 8
OSC_RES 12
MCLK 11
19
SDA 20
AVSS 5
DEVICE
CONTROL
DIGITAL
AUDIO
PROCESSOR
POWER
SUPPLY
SUPPLY
SCL 21
AVSS_PWM
51
AVDD_PWM
50
PWM_P_1
39
PWM_M_1
38
PWM_P_2
41
PWM_M_2
40
PWM_P_3
43
PWM_M_3
42
N.C.
45
N.C.
44
N.C.
47
N.C.
46
PWM_P_4
49
PWM_M_4
48
N.C.
54
N.C.
53
N.C.
56
N.C.
55
LRCLKO
31
SCLKO
30
PSVC
33
VALID
37
TEST
32
SDOUT
29
VR_RWM
52
DVSS1_CORE
36
DVDD1_CORE
35
BKND_ERR
34
PWM
SECTION
• IC Block Diagrams
– REAR MAIN Board –
IC8103 BD33HA5WEFJ-E2 (SA-SLRT5)
IC9103 BD33HA5WEFJ-E2 (SA-SRRT5)
IC8103 BD33HA5WEFJ-E2 (SA-SLRT5)
IC9103 BD33HA5WEFJ-E2 (SA-SRRT5)
IC8202 TAS5534DGGR (SA-SLRT5)
IC9202 TAS5534DGGR (SA-SRRT5)
IC9202 TAS5534DGGR (SA-SRRT5)
VIN
1
VC
2
VO
3
VADJ
4
GND
5
REGULATOR
IC8171 PQ200WNA1ZVU (SA-SLRT5)
IC9171 PQ200WNA1ZVU (SA-SRRT5)
IC9171 PQ200WNA1ZVU (SA-SRRT5)
SA-SLRT5/SRRT5
27
GVDD_AB 1
VDD 2
OC_ADJ 3
RESET 4
INPUT_A 5
PVDD_CD
OUT_C
31
PVDD_CD
30
32
PVDD_CD
29
GND
33
INPUT_B 6
C_START 7
GND 9
GND 11
GND 10
GND 12
AVDD 13
INPUT_C 14
INPUT_D 15
OTW 17
PROTECTION
&
I/O LOGIC
+
–
–
+
–
–
+
–
–
TEMP
SENSE
STARTUP
CONTROL
AVDD
DVDD 8
DVDD
POWER-UP
RESET
CB3C OVER-LOAD
PROTECTION
UVP
GATE-
DRIVE
DRIVE
+
–
–
GATE-
DRIVE
DRIVE
GND
OUT_B
34
35
PVDD_AB
38
GND
42
GND
41
BST_A
44
BST_B
43
GATE-
DRIVE
DRIVE
PVDD_AB
36
PVDD_AB
37
OUT_A
39
OUT_A
40
OUT_D
27
GND
26
GND
25
BST_C
24
BST_D
23
OUT_D
28
PWM & TIMING
CONTROL
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
PWM & TIMING
CONTROL
PWM & TIMING
CONTROL
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM & TIMING
CONTROL
GATE-
DRIVE
DRIVE
CLIP 18
FAULT 16
M3 21
M2 20
M1 19
GVDD_CD 22
BST_X
GVDD_X
AVDD
DVDD
GVDD_X
AVDD
DVDD
IC8203 TAS5614LA (SA-SLRT5)
IC9203 TAS5614LA (SA-SRRT5)
IC9203 TAS5614LA (SA-SRRT5)
IC8402 PST8429UL (SA-SLRT5)
IC9402 PST8429UL (SA-SRRT5)
IC9402 PST8429UL (SA-SRRT5)
GND 1
VDD 2
+
–
–
VREF
OUT
4
CD
3
SA-SLRT5/SRRT5
28
• IC Pin Function Description
REAR MAIN BOARD IC8400 MB9AF142LBPMC1-G-JNE2 (SYSTEM CONTROLLER) (SA-SLRT5)
IC9400 MB9AF142LBPMC1-G-JNE2 (SYSTEM CONTROLLER) (SA-SRRT5)
Pin No.
Pin Name
I/O
Description
1
VCC
-
Power supply terminal (+3.3V)
2
DC_DET
I
Speaker DC detection signal input terminal “L”: speaker DC is detected
3
DRIVER_SD
I
Shutdown signal input from the digital power amplifi er “L”: shutdown
4
P_DAMP_CLIP
I
Clipping warning signal input from the digital power amplifi er “L”: clipping
5
-
-
Not used
6
TAS5534_SCL
O
Serial data transfer clock signal output to the stream processor
7
TAS5534_SDA
I/O
Two-way data bus with the stream processor
8
-
-
Not used
9
TAS5534_XPDN
O
Power down signal output to the stream processor “L”: power down
10
TAS5534_XRST
O
Rest signal output to the stream processor “L”: reset
11
TAS5534_MUTE
O
Muting on/off control signal output to the stream processor “L”: muting on
12
LED_REAR
-
Not used
13
P_CONT_ACDET
O
Not used
14
LED_RED
O
LED drive signal output terminal for the on/standby indicator (red) “H”: LED on
15
LED_GREEN
O
LED drive signal output terminal for the on/standby indicator (green) “H”: LED on
16
VSS
-
Ground terminal
17
C
-
External capacitor connection terminal
18
VCC
-
Power supply terminal (+3.3V)
19, 20
-
-
Not used
21
INITX (RESET)
I
System reset signal input terminal “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
22, 23
-
-
Not used
24
WS_RST
O
Reset signal output to the RF modulator “L”: reset
25
WS_SCL
O
Serial data transfer clock signal output to the RF modulator
26
WS_SDA
I/O
Two-way data bus with the RF modulator
27
WS_INT
I
Interrupt signal input from the RF modulator
28
MD1
I
Mode selection signal input terminal “L”: fl ash memory writing mode
29
MD0
I
Mode selection signal input terminal “H”: fl ash memory writing mode
30
X0
I
System clock input terminal (4 MHz)
31
X1
O
System clock output terminal (4 MHz)
32
VSS
-
Ground terminal
33
VCC
-
Power supply terminal (+3.3V)
34
KEY_PAIRING
I
SECURE LINK key input terminal
35
KEY_POWER
I
Power key input terminal
36
MODEL
I
Model setting terminal
37
DEST
I
Destination setting terminal
38
Pull Up Power
O
Power supply control terminal for the destination setting
39
KEY_REAR
-
Not used
40
AC_CUT
I
AC cut detection signal input terminal “L”: AC cut is detected
41
AVCC
-
Power supply terminal (+3.3V)
42
AVRH
I
Reference voltage (+3.3V) input terminal
43
AVSS
-
Ground terminal
44, 45
P_CONT1, P_CONT2
O
Power on/off control signal output terminal “H”: power on
46
ON CHIP DEBUG/
CLK1
I
Serial data transfer clock signal input terminal for fl ash memory writing
47
(PROG VUTX)
O
Serial data output terminal for fl ash memory writing
48
(PROG VURX)
I
Serial data input terminal for fl ash memory writing
49
-
-
Not used
50
TCK
I
Test clock signal input terminal (for JTAG) Not used
51
TDI
I
Test data input terminal (for JTAG) Not used
52
TMS
I
Test mode selection signal input terminal (for JTAG) Not used
53
TDO
O
Test data output terminal (for JTAG) Not used
54 to 59
-
-
Not used
60
PVDD_STBY
O
Power standby signal output to the switching regulator “H”: power on
61
VCC
-
Power supply terminal (+3.3V)
62
PVDD_SD_EN
O
Not used
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