DOWNLOAD Sony NWD-E023F / NWD-E025F Service Manual ↓ Size: 1.15 MB | Pages: 32 in PDF or view online for FREE

Model
NWD-E023F NWD-E025F
Pages
32
Size
1.15 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
nwd-e023f-nwd-e025f.pdf
Date
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Sony NWD-E023F / NWD-E025F Service Manual ▷ View online

NWD-E023F/E025F
21
Pin No.
Pin Name
I/O
Description
108 (V2)
HPREF
-
Not used
109 (V10)
CSOFT
-
Not used
110 (U5)
TESTAUD
-
Not used
111 (W3)
DGND
-
Ground terminal
112 (U1)
DVDD
-
Power supply terminal (+2.8V)
113 (U9)
ARST
O
System reset signal output terminal
114 (U6)
AVDOSC1
-
Power supply terminal (+1.2V)
115 (W4)
EXTAL
I
Main system clock input terminal (45.1584 MHz)
116 (W5)
XTAL
O
Main system clock output terminal (45.1584 MHz)
117 (P9)
AVSOSC
-
Ground terminal
118 (W8)
TEX
I
Sub system clock input terminal (12 MHz)
119 (W9)
TX
O
Sub system clock output terminal (12 MHz)
120 (R9)
AVDOSC2
-
Power supply terminal (+1.2V)
121 (U8)
AVSPLL
-
Ground terminal
122 (R10)
AVDPLL
-
Power supply terminal (+1.2V)
123 (U10)
AVDUSB
-
Power supply terminal (+3.3V)
124 (U11)
AVSUSB
-
Ground terminal
125 (W13)
DP
I/O
Two-way USB communication (+) data bus with the USB connector
126 (W12)
DM
I/O
Two-way USB communication (-) data bus with the USB connector
127 (P10)
VBUS/GPIOD0
I
USB power supply voltage detection signal input from the power control
128 (N10)
TxD0/GPIOI0
O
Not used
129 (G10)
RxD0/GPIOI1
I
Not used
130 (U12)
TxD1/GPIOJ0
O
Not used
131 (R11)
RxD1/GPIOJ1
I
Not used
132 (U13)
SI0/GPIOG1
I
Serial data input from the tuner
133 (P11)
SO0/GPIOG0
O
Serial data output to the tuner
134 (R13)
SCK0
O
Serial data transfer clock signal output to the tuner
135 (R12)
SCS0/GPIOG2
O
Serial data latch pulse signal output to the tuner
136 (V13)
SI1/GPIOH1
I
Serial data input from the real time clock
137 (V12)
SO1/GPIOH0
O
Serial data output to the real time clock
138 (V14)
SCK1
O
Serial data transfer clock signal output to the real time clock
139 (V15)
SCS1/GPIOH2
O
Not used
140 (M10)
DVS
-
Ground terminal
141 (U14)
DVDIO1
-
Power supply terminal (+2.8V)
142 (P12)
DVDIO1
-
Power supply terminal (+2.8V)
143 (W10)
DVS
-
Ground terminal
144 (U16)
DVDK1
-
Power supply terminal (+1.2V)
145 (W11)
DVS
-
Ground terminal
146 (W15)
FS256
O
Not used
147 (W16)
LRCK/WS
O
Not used
148 (W17)
BCK/SCK
O
Not used
149 (V16)
ADDT/SDI/GPIOM0
O
Not used
150 (U15)
DADT/SDO/GPIOM1
O
Not used
151 (V17)
MUTFGL/GPIOM2
O
Not used
152 (V18)
MUTFGR/GPIOM3
O
Model setting terminal    Fixed at "L" in this set
153 (W14)
DVS
-
Ground terminal
154 (P17)
DVDIO2
-
Power supply terminal (+2.8V)
155 (P13)
DVDIO2
-
Power supply terminal (+2.8V)
156 (N17)
DVS
-
Ground terminal
157 (P18)
DVDK2
-
Power supply terminal (+1.2V)
158 (R187)
DVS
-
Ground terminal
159 (N11)
NBOOT
I
Not used
160 (T18)
A0/GPIOA0
O
Not used
161 (R14)
A1
O
Address signal output to the fl ash ROM & S-RAM
162 (P14)
A2
O
Address signal output to the fl ash ROM & S-RAM
163 (P15)
A3
O
Address signal output to the fl ash ROM & S-RAM
NWD-E023F/E025F
22
Pin No.
Pin Name
I/O
Description
164 (U17)
A4
O
Address signal output to the fl ash ROM & S-RAM
165 (K12)
A5
O
Address signal output to the fl ash ROM & S-RAM
166 (T17)
A6
O
Address signal output to the fl ash ROM & S-RAM
167 (L13)
A7
O
Address signal output to the fl ash ROM & S-RAM
168 (N14)
A8
O
Address signal output to the fl ash ROM & S-RAM
169 (M14)
A9
O
Address signal output to the fl ash ROM & S-RAM
170 (N15)
A10
O
Address signal output to the fl ash ROM & S-RAM
171 (K13)
A11
O
Address signal output to the fl ash ROM & S-RAM
172 (R17)
A12
O
Address signal output to the fl ash ROM & S-RAM
173 (L14)
A13
O
Address signal output to the fl ash ROM & S-RAM
174 (M15)
A14
O
Address signal output to the fl ash ROM & S-RAM
175 (J13)
A15
O
Address signal output to the fl ash ROM & S-RAM
176 (L15)
A16
O
Address signal output to the fl ash ROM & S-RAM
177 (U19)
AGND
-
Ground terminal
178 (U18)
ADVREF
O
Reference voltage output terminal    Not used
179 (T19)
AVDD
-
Power supply terminal (+2V)
180 (R19)
SUBGND
-
Ground terminal
181 (P19)
MICOUTL
O
Microphone signal (L-ch) output terminal    Not used
182 (N19)
MICOUTR
O
Microphone signal (R-ch) output terminal    Not used
183 (N18)
MICINL
I
Audio signal (L-ch) input from the tuner
184 (M18)
MLININL
I
Audio signal (L-ch) input terminal    Not used
185 (M19)
MICVREF
O
Reference voltage output terminal    Not used
186 (L19)
MICINR
I
Audio signal (R-ch) input from the tuner
187 (K19)
MLININR
I
Audio signal (R-ch) input terminal    Not used
188 (G18)
T_ADINR
I
Not used
189 (L17)
DVS
-
Ground terminal
190 (E10)
DVDIO2
-
Power supply terminal (+2.8V)
191 (M17)
DVDIO2
-
Power supply terminal (+2.8V)
192 (L18)
DVS
-
Ground terminal
193 (C10)
DVDK2
-
Power supply terminal (+1.2V)
194 (G11)
DVS
-
Ground terminal
195 (K15)
A17
O
Address signal output to the fl ash ROM & S-RAM
196 (K17)
A18
O
Address signal output to the fl ash ROM & S-RAM
197 (J14)
A19
O
Address signal output to the fl ash ROM & S-RAM
198 (J15)
A20
O
Address signal output to the fl ash ROM & S-RAM
199 (H14)
A21
O
Address signal output to the fl ash ROM & S-RAM
200 (K14)
A22
O
Address signal output terminal    Not used
201 (E11)
A23/GPIOA1
I/O
Not used
202 (G14)
A24/GPIOA2
I
Model setting terminal    Fixed at "L" in this set
203 (H15)
A25/GPIOA3
I
Model setting terminal    Fixed at "L" in this set
204 (J17)
D0
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
205 (C11)
D1
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
206 (F11)
D2
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
207 (E12)
D3
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
208 (H18)
D4
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
209 (H17)
D5/GPIOA9 
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
210 (G17)
D6/GPIOA910
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
211 (F14)
D7/GPIOA11
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
212 (J19)
DVS
-
Ground terminal
213 (J18)
DVDIO2
-
Power supply terminal (+2.8V)
NWD-E023F/E025F
23
Pin No.
Pin Name
I/O
Description
214 (K18)
DVDIO2
-
Power supply terminal (+2.8V)
215 (F12)
DVS
-
Ground terminal
216 (C12)
DVDK2
-
Power supply terminal (+1.2V)
217 (C13)
DVS
-
Ground terminal
218 (H19)
RTCVDD
-
Power supply terminal
219 (G19)
RTCREGO
O
Power supply (+2.8V) output to the real time clock
220 (F19)
RTCVREF
O
Reference voltage output terminal    Not used
221 (E19)
RTCGND
-
Ground terminal
222 (G15)
D8/GPIOA12
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
223 (E13)
D9/GPIOA13
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
224 (F13)
D10/GPIOA14
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
225 (F15)
D11/GPIOA15
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
226 (F18)
D12/GPIOA16
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
227 (E14)
D1/GPIOA17
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
228 (B13)
D14/GPIOA18
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
229 (B14)
D15/GPIOA19
I/O
Two-way data bus with the fl ash ROM & S-RAM and serial data output to the liquid crystal 
display unit
230 (E17)
WAIT/GPIOA20
O
Power supply on/off control signal output terminal
231 (F17)
CS0/GPIOA2
O
Chip select signal output to the fl ash ROM & S-RAM
232 (E18)
CS1/GPIOA22
O
Chip select signal output to the fl ash ROM & S-RAM
233 (C14)
CS2/GPIOA23
O
Chip select signal output to the liquid crystal display unit
234 (D17)
CS3/GPIOA24
I/O
Not used
235 (B17)
CS4/GPIOA25
O
Clock signal output to the tuner
236 (D19)
RE/GPIOA26
O
Read signal output to the fl ash ROM & S-RAM
237 (C15)
WE/GPIOA27
O
Write signal output to the fl ash ROM & S-RAM
238 (D18)
LB/GPIOA28
O
Lower byte access strobe signal output to the fl ash ROM & S-RAM
239 (C17)
UB/GPIOA29
O
Upper byte access strobe signal output to the fl ash ROM & S-RAM
240 (C18)
DVDK2
-
Power supply terminal (+1.2V)
241 (B16)
DVS
-
Ground terminal
242 (A16)
DVS
-
Ground terminal
243 (C16)
DVDIO2
-
Power supply terminal (+2.8V)
244 (A17)
DVDIO2
-
Power supply terminal (+2.8V)
245 (B18)
DVS
-
Ground terminal
246 (B15)
INTR
I
Interrupt request signal input terminal    Not used
247 (C19)
RTCVSB
-
Power supply terminal (+2.8V)
248 (A15)
OSCIN
I
Clock signal (32.768 kHz) input from the real time clock
249 (A14)
OSCOUT
O
Clock signal  (32.768 kHz) output terminal    Not used
250 (A13)
CLK32KOUT
O
Clock signal output terminal    Not used
251 (A12)
DSUBGND
-
Ground terminal
252 (A11)
DRAIN
O
Power supply (+2.8V) output to the NAND fl ash ROM
253 (B12)
DVS
-
Ground terminal
254 (B10)
DVDIO0
-
Power supply terminal (+2.8V)
255 (B9)
DVDK0
-
Power supply terminal (+1.2V)
256 (B11)
DVS
-
Ground terminal
257 (A10)
SOURCE
I
Power supply (+2.8V) input terminal for NAND fl ash ROM
258 (A9)
GATE
I
Power supply on/off control signal input terminal for the NAND fl ash ROM
259 (B8)
CRST1A
I
RESET switch input terminal
260 (B7)
CRST1B
I
Reset signal input terminal    Not used
261 (A8)
RST1VDD
-
Power supply terminal (+2.8V)
262 (A7)
RST1AOUT
O
System reset signal output terminal
263 (A6)
RST1BOUT
O
Reset signal output terminal    Not used
NWD-E023F/E025F
24
Pin No.
Pin Name
I/O
Description
264 (A5)
RSTGND
-
Ground terminal
265 (A4)
RST
O
System reset signal output terminal
266 (A1)
NC
O
Not used
267 (A19)
NC
O
Not used
268 (E5)
NC
O
Not used
269 (E15)
NC
O
Not used
270 (R5)
NC
O
Not used
271 (R15)
NC
O
Not used
272 (W1)
NC
O
Not used
273 (W19)
NC
O
Not used
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