Sony NWD-E023F / NWD-E025F Service Manual ▷ View online
NWD-E023F/E025F
17
• IC Block Diagrams
– MAIN Board –
IC401 NCP5612MUTBG
V bat
CHARGE PUMP
DC/DC CONVERTER
Q1
Q2
OVERVOLTAGE
CURRENT MIRRORS
V bat
DIGIT AL CONTROL
NC
CNTL
IREF
LED/ICON
LED1
ANALOG CONTROL
OVERTEMPERATURE
V bat
GND
GND
150 k
12
10
9
8
7
2
3
6
1
4
5
11
Vo
ut
C2P
C2N
C1P
VBA
T
C1N
GND
1
USB_SUS
22 IU4
23 PG_IO
24 LX_IO
25 IN_IO
26 OUT_CORE
27 IN_CORE
28 LX_CORE
29 PG_AORE
30 EN
21 OUT_IO
USB POWER
MANAGEMENT
2
USB_H/L
3
USB_IN1
4
USB_IN2
5
SYS1
6
SYS2
7
BAT1
8
BAT2
9
XCHG_STAT
10
XCHG_EN
33
IU6
34
IN_USB3.3
35
OUT_USB3.3
36
VL
37
IU7
38
IU8
39
IU9
40
USB_POK
41
SHEELD
32
XCHG_FL
T
31
IU5
11
THM
12
CHG_ISET
13
CT
14
GND
15
IU1
16
IN_AD
17
OUT_AD
18
IU2
19
BP
20
IU3
CORE
STEP-DOWN
REGULATOR
REGULATOR
I/O
STEP-DOWN
REGULATOR
REGULATOR
REF
1MHz OSC
LI+BATTERY
CHARGER
AND
SYS LOAD SWITCH
USB LDO 3.3V
REGURATOR
REG5
3.3V
A/D LDO 2.0V
REGURATOR
REGURATOR
SEQUENCER
(FIGURE 7)
INPUT LIMITER
AND
CHARGER THERMAL
REGULATION
THERMAL-OVERLOAD
PROTECTION ABOVE TJ=+165 C
PWM
IC601 MAX8670A
NWD-E023F/E025F
18
FCON 2
GND 1
N.C. 3
OUTPUT
CONTROLLER
BUS
INTERFACE
CIRCUIT
N.C.
14
N.C.
15
N.C.
16
N.C.
17
N.C.
18
N.C.
19
N.C.
20
N.C.
21
N.C.
22
CE 1 4
DATA 5
CLK 6
/AIRQ 8
/TIRQ 7
CE 0 9
INTERRUPTS
CONTROLLER
CLOCK &
CALENDER
TIMER
REGISTER
ALARM
REGISTER
FOUT 10
VDD 11
SHIFT
REGISTER
CONTROL
REGISTER
DIVIDER
OSC
32.768kHz
CONTROL LINE
1
VCC
11 X2
10 X1
10 X1
9 CL
8 LA
8 LA
2
ANT
3
GND
4
RSSO
14
GND
13
ST
O
12
D-GND
5
AUDIO RIGHT
6
AUDIO LEFT
7
DA
RSSI
LIMITER
DEMODULATOR
MPX DECODER
BUFFER
IF
FILTER
TUNING
SYSTEM
IF
LOGIC
ANTENNA
BALUN
LAG-LEAD
FILTER
VCO
1
VIN
2
GND
3
VOUT
4 NC
5 GND
6 VCONT
VOLTAGE
REFERENCE
ON/OFF
CONTROL
THERMAL
&
OVERCURRENT
PROTECTION
–
+
+
IC801 RTC-4574NB
IC2702 SDFMM1N23GB2T
IC2704 TK63727HCL-G
NWD-E023F/E025F
19
• IC Pin Function Description
MAIN BOARD IC101 CXD5090B1-003GG (CPU)
Pin No.
Pin Name
I/O
Description
1 (A3)
NAD0/GPIOC0
I/O
Two-way data signal bus with the NAND fl ash ROM
2 (C3)
NAD1/GPIOC1
I/O
Two-way data signal bus with the NAND fl ash ROM
3 (B2)
NAD2/GPIOC2
I/O
Two-way data signal bus with the NAND fl ash ROM
4 (B4)
NAD3/GPIOC3
I/O
Two-way data signal bus with the NAND fl ash ROM
5 (B5)
NAD4/GPIOC4
I/O
Two-way data signal bus with the NAND fl ash ROM
6 (B6)
NAD5/GPIOC5
I/O
Two-way data signal bus with the NAND fl ash ROM
7 (C2)
NAD6/GPIOC6
I/O
Two-way data signal bus with the NAND fl ash ROM
8 (C4)
NAD7/GPIOC7
I/O
Two-way data signal bus with the NAND fl ash ROM
9 (C5)
NCLE/GPIOC8
O
Command latch enable signal output to the NAND fl ash ROM
10 (C6)
NALE/GPIOC9
O
Address latch enable signal output to the NAND fl ash ROM
11 (D3)
NCE0/GPIOC10
O
Chip enable signal output to the NAND fl ash ROM
12 (E6)
NCE1/GPIOC11
O
Chip enable signal output to the NAND fl ash ROM
13 (F3)
NCE2/GPIOC12
O
Battery power supply voltage detection on/off control signal output terminal
14 (C7)
NCE3/GPIOC13
I/O
Not used
15 (E3)
NRE/GPIOC14
O
Read signal output to the NAND fl ash ROM
16 (C8)
NWE/GPIOC15
O
Write signal output to the NAND fl ash ROM
17 (F2)
NWP/GPIOC16
O
Write protection signal output to the NAND fl ash ROM
18 (C9)
NRB0/GPIOC17
O
Read/Busy signal output to the NAND fl ash ROM
19 (F5)
NRB1/GPIOC18
O
Read/Busy signal output to the NAND fl ash ROM
20 (G3)
NRB2/GPIOC19
I/O
Not used
21 (E2)
NRB3/GPIOC20
I/O
Not used
22 (F6)
DVS
-
Ground terminal
23 (G2)
DVDIO2
-
Power supply terminal (+2.8V)
24 (E7)
DVDIO2
-
Power supply terminal (+2.8V)
25 (E8)
DVS
-
Ground terminal
26 (G5)
DVDK2
-
Power supply terminal (+1.2V)
27 (H2)
DVS
-
Ground terminal
28 (B3)
CRST2
I
Reset signal input terminal Not used
29 (C1)
RST2OUT
O
Reset signal output to the power control
30 (D1)
RST2VDD
-
Power supply terminal
31 (D2)
T_ADINL
I
Not used
32 (E1)
HPVDD
-
Power supply terminal (+2V)
33 (F1)
HPOUTL
O
Audio signal (L-ch) output to the headphone jack
34 (G1)
PVDD
-
Power supply terminal (+2V)
35 (H1)
PGND
-
Ground terminal
36 (J1)
HPOUTR
O
Audio signal (R-ch) output to the headphone jack
37 (K1)
HPGND
-
Ground terminal
38 (G6)
GPION0/INT8
I
Key wake up signal input terminal
39 (H3)
GPION1/INT9
I
HOLD switch input terminal
40 (F7)
GPION2/INT10
I
Folder, HOME key input terminal
41 (J2)
GPION3/INT11
I
Playback key input terminal
42 (E9)
TDI
I
Data input terminal (for JTAG) Not used
43 (J3)
TMS
I
Mode selection signal input terminal (for JTAG) Not used
44 (H5)
TCK
I
Clock signal input terminal (for JTAG) Not used
45 (K2)
TDO
O
Data output terminal (for JTAG) Not used
46 (H6)
TRST
I
Reset signal input terminal (for JTAG)
47 (F8)
TEST
I
Boot control signal input terminal Not used
48 (G7)
EVA
I
EVA/FLASH modes selection signal input terminal Not used
49 (K3)
TREQA
I
Request signal input terminal (for JTAG) Not used
50 (J5)
TACK
O
Request signal output terminal (for JTAG) Not used
51 (F9)
SCL/GPIOK0
O
USB suspend control signal output to the power control
52 (J6)
SDA/GPIOK1
I/O
Not used
53 (L3)
EC0/INT6/GPIOL0
I/O
Not used
NWD-E023F/E025F
20
Pin No.
Pin Name
I/O
Description
54 (F10)
T1/GPIOL1
I/O
Not used
55 (M3)
EC2/INT7/GPIOL2
I/O
Not used
56 (K5)
T3/GPIOL3
O
Power supply on/off control signal output terminal for NAND fl ash ROM
57 (K6)
BEEP/GPIOL4
I/O
Not used
58 (H10)
PWM/SUSPEND/
GPIOL5
O
Power supply on/off control signal output to the LED driver for liquid crystal display unit back
light
light
59 (N3)
DVS
-
Ground terminal
60 (L5)
DVDIO2
-
Power supply terminal (+2.8V)
61 (L6)
DVDIO2
-
Power supply terminal (+2.8V)
62 (J7)
DVS
-
Ground terminal
63 (P2)
DVDK2
-
Power supply terminal (+1.2V)
64 (M5)
DVS
-
Ground terminal
65 (L2)
BEEPEN
I
Beep signal input terminal Not used
66 (L1)
HPINL
I
Audio signal (for headphone L-ch) input terminal
67 (M1)
HPLININL
I
Audio signal (for microphone L-ch) input terminal Not used
68 (M2)
HPINR
I
Audio signal (for headphone R-ch) input terminal
69 (N2)
HPLININR
I
Audio signal (for microphone R-ch) input terminal Not used
70 (M6)
AVDLPF
-
Power supply terminal (+2V) (for low-pass fi lter)
71 (N1)
VREFL
O
Reference voltage output terminal for headphone amplifi er (L-ch) Not used
72 (P1)
AOUTL
O
Audio signal (for headphone L-ch) output terminal
73 (R1)
AOUTR
O
Audio signal (for headphone R-ch) output terminal
74 (T1)
VREFR
O
Reference voltage output terminal for headphone amplifi er (R-ch) Not used
75 (P3)
AVSLPF
-
Ground terminal (for low-pass fi lter)
76 (R3)
AVDADC
-
Power supply terminal (+1.2V)
77 (R2)
AN0
I
Key input terminal (A/D input)
78 (T2)
AN1
I
Not used
79 (U2)
AN2
I
Not used
80 (V3)
AN3
I
Not used
81 (V5)
AN4
I
Not used
82 (V6)
AN5
I
Not used
83 (V4)
AN6
I
Not used
84 (V7)
AN7
I
Battery power supply voltage detection signal input terminal
85 (T3)
AVSADC
-
Ground terminal
86 (N5)
SDCLK
O
Not used
87 (U3)
SDCMD/INT1/GPIOF0
I
Interrupt signal input from the real time clock
88 (K7)
SDDAT0/DREQ/INT2/
GPIOF1
O
Chip enable signal output to the real time clock
89 (P5)
SDDAT1/DACK/INT3/
GPIOF2
I
PLAYMODE, SOUND key input terminal
90 (N6)
SDDAT2/INT4/GPIOF3
O
Data control signal output to the liquid crystal display unit
91 (U4)
SDDAT3/INT5/GPIOF4
O
Reset signal output to the liquid crystal display unit
92 (K8)
DVS
-
Ground terminal
93 (P6)
DVDIO2
-
Power supply terminal (+2.8V)
94 (R6)
DVDK2
-
Power supply terminal (+1.2V)
95 (W6)
DVS
-
Ground terminal
96 (L7)
DVDIO2
-
Power supply terminal (+2.8V)
97 (W7)
DVS
-
Ground terminal
98 (P7)
MSBS/INT0/GPIOE0
O
Not used
99 (R7)
MSSCLK
O
Not used
100 (N9)
MSDIO0/GPIOE1
O
Not used
101 (U7)
MSDIO1/GPIOE2
O
Battery charge control signal output to the power control
102 (P8)
MSDIO2/GPIOE3
O
USB power supply control signal output to the power control
103 (R8)
MSDIO3/GPIOE4
I
Battery charge start signal input from the power control
104 (G9)
MSINS/GPIOE5
I
Not used
105 (V11)
MCSEL
I
Not used
106 (V8)
CBIAS
-
Not used
107 (V9)
CCOM
-
Not used
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