Sony NW-S4 Service Manual ▷ View online
NW-S4
18
18
FB302
Q202
Q102
Q101
Q201
D803
R835
CN805
D804
R836
R837
D805
S804
C310
C313
C101
C301
C805
C806
C102
C202
C303
C304
C306
C311
C312
D201
D101
D808
D811
FB301
IC302
IC301
L301
Q301
Q302
R101
R102
R103
R104
R105
R106
R202
R203
R204
R205
R206
R803
R802
CN803
CN601
CN804
C814
C810
C808
C807
C315
C314
C307
C305
C302
C201
D810
D809
D812
D813
D806
D807
R832
R834
R833
R804
R805
R817
R818
R306
R305
R304
R303
R302
R301
R201
CN802
SUB BOARD
(COMPONENT SIDE)
(11)
11
1-681-434-
LCD901
LIQUID CRYSTAL DISPLAY
SUB BOARD
(CONDUCTOR SIDE)
KEY FLEXIBLE BOARD
JACK FLEXIBLE
MODULE
MODULE
A
MAIN BOARD
CN801
S805
S805
S806
S801
S802
1
2
3
4
5
CN807
11
1-678-604-
+
–
VOL
MODE
>
S806
S801
S802
MEGA BASS
.
J301
(HEAD PHONE)
i
9
8
7
7
6
5
5
4
3
2
1
3
2
1
CN602
AVLS
S807
SHIFT
S803
HOLD
S808
NORM
LIMIT
HOLD
OFF
(11)
11
1-681-434-
1
2
CN806
B2
E
B1
C2
C1
C1
B
C2
E1
E2
S
S
D
D
D
D
G
G
S
G
S
G
D803 – 805
(LCD BACK LIGHT)
Nx
MODE FLEXIBLE
MODULE
MODULE
A
B
C
D
E
F
G
1
2
3
4
5
6
7
8
9
10
4-6.
PRINTED WIRING BOARDS – SUB Board –
D101
B-5
D201
B-5
D803
A-6
D804
A-7
D805
A-8
D806
E-4
D807
E-4
D808
A-10
D809
E-4
D810
E-3
D811
A-9
D812
F-3
D813
F-3
IC301
B-1
IC302
B-2
Q101
B-4
Q102
B-4
Q201
A-4
Q202
A-4
Q301
A-2
Q302
A-3
• Semiconductor
Location
Ref. No.
Location
(Page 15)
NW-S4
19
19
4-7.
SCHEMATIC DIAGRAM – SUB Board –
•
See page 14 for Waveforms.
•
See page 20 for IC Block Diagram.
(Page 17)
NW-S4
20
20
1
2
3
4
5
6
7
8
SERIAL
PORT
DE-
EMPHASIS
HEADPHONE
AMP
DIGITAL
FILTERS
FILTERS
∆∑
DAC
ANALOG
FILTER
DIGITAL
VOLUME
CONTROL
BASS/TREBLE
BOOST
LIMITING
ANALOG
VOLUME
CONTROL
∆∑
DAC
ANALOG
FILTER
ANALOG
VOLUME
CONTROL
14
13
16
15
12
11
10
9
CONTROL PORT
LRCK
SDATA
SCLK
VD/IO
MCLK
SCL
VQ HP
REF GND
HP B
VA HP
RST
SDA
VA
GND
HP A
FILT+
8
15
16
10
14 13 12 11
G
A
B
Y0 Y1 Y2 Y3
9
6
7
4
5
2
3
1
G
A
B
Y0 Y1 Y2 Y3
VCC
2G (ENABLE)
2Y0
2Y1
2Y2
2Y3
2A
2B
1Y0
1Y1
1Y2
1Y3
1A
1B
GND
1G (ENABLE)
SELECT DATA OUTPUTS
SELECT DATA OUTPUTS
–
+
+
–
+
+
1
2
3
4
5
REFERENCE
LOW-BATTERY
COMPARATOR
ERROR
AMP
Q
ONE-SHOT
TRIG
–
+
+
EN
8
7
6
S
Q
R
F/F
+
–
–
ZERO CROSSING
AMP
Q
ONE-SHOT
TRIG
MINIMUM
OFF-TIME
ONE-SHOT
MAXIMUM
ON-TIME
OFF-SHOT
CURRENT-LIMIT
AMP
LBI
FB
REF
LBO
OUT
LX
GND
SHDN
+
–
+ –
CONTROL
AND
DRIVER
LOGIC
+
–
+
–
+ –
+ –
CHIP
SUPPLY
+
–
+
–
+
–
–
+
–
+
–
FB
REF
SLOPE COMPENSATION
+
–
+
–
–
+ –
FB
REF
40mV
OVERVOLTAGE
COMPARATOR
PWM ON
SIGNAL
SYNC
CELL
RAMP
GEN
REFERENCE
VOLTAGE
PWM
PGND
LX
SHDN
SYNC/
PWM
PWM
LIM
10
9
8
7
6
0.1X
SENS
FET
0.1X
SENS
FET
5mA 2N PFM
ADJ.IN PWM
ADJ.IN PWM
PFM CURRENT
COMPARATOR
COMPARATOR
LIM
COMPARATOR
NEGLIM
COMPARATOR
12mV
120mV
PWM
COMPARATOR
REF
ON
PFM
COMPARATOR
IN
BP
GND
REF
FB
1
2
3
4
5
P
N
• IC Block Diagrams
– MAIN Board –
– MAIN Board –
IC401
MAX1674EUA-TG069
IC404
MAX1692EUB-TG069
IC604
SN74LV139ADGVR
IC901
ML60851CLBZ060 (Not supplied part)
– SUB Board –
IC302
CS4343-KSR
1
32
33
31 30 29 28 27 26 25
24 23
34
35
36
37
38
39
40
41
42
43
44
1
2
3 4 5 6
7
8 9 10 11
22
21
20
19
18
17
16
15
14
13
12
END POINT FIFO/
8BYTE SET-UP
REGISTER
STATUS/
CONTROL
PROTOCOL
ENGINE
USB
TRANSCEIVER
DPLL
OSC
APPLICATION
INTERFACE
DREQ
AD7
AD6
AD5
AD4
GND
VCC5
AD3
AD2
AD1
AD0
D+
D
–
VCC3
TEST1
TEST2
XIN
XOUT
CS
RD
WR
RESET
INTR
D15
D14
D13
D12
GND
VCC5
D11
D10
D9
D8
ALE
ADSEL
A7
A6
A5
A4
A3
A2
A1
A0
DACK
21
NW-S4
4-8.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC601 TMS320DA150GGU120 (DIGITAL SIGNAL PROCESSOR) (Not supplied part)
Pin No.
Pin Name
I/O
Description
1
CVSS
—
Ground terminal
2
A22
—
Address signal terminal Not used (open)
3
CVSS
—
Ground terminal
4
DVDD
—
Power supply terminal (+3.2V)
5
A10
—
Address signal terminal Not used (open)
6
HD7
O
Muting control signal output terminal “L”: muting
7 to 10
A11 to A14
I
Address signal input terminal Not used (open)
11
A15
O
Read/write signal output to the 2 to 4 decoder (IC604)
12
CVDD
—
Power supply terminal (+1.5V)
13
HAS
I
Address strobe signal input terminal Not used (fixed at “H”)
14
DVSS
—
Ground terminal
15
CVSS
—
Ground terminal
16
CVDD
—
Power supply terminal (+1.5V)
17
HCS
I
Chip select signal input terminal Not used (fixed at “H”)
18
HR/W
I
Read/write signal input terminal Not used (fixed at “H”)
19
READY
I
Data ready signal input terminal Not used (fixed at “H”)
20
PS
O
Program space select signal output terminal Not used (open)
21
DS
O
Data space select signal output terminal Not used (open)
22
IS
O
I/O space select signal output to the USB controller (IC901)
23
R/W
O
Read/write signal output to the 2 to 4 decoder (IC604)
24
MSTRB
O
Memory strobe signal output terminal Not used (open)
25
IOSTRB
O
I/O strobe signal output to the 2 to 4 decoder (IC604)
26
MSC
O
Microstate complete signal output terminal Not used (open)
27
XF
O
External flag signal output terminal Not used (open)
28
HOLDA
O
Hold acknowledge signal output terminal Not used (open)
29
IAQ
O
Instruction acquisition signal output terminal Not used (open)
30
HOLD
I
Hold signal input terminal Not used (fixed at “H”)
31
BIO
I
Branch control signal input terminal Not used (fixed at “H”)
32
MP/MC
I
Mode select signal input terminal Not used (fixed at “L”)
33
DVDD
—
Power supply terminal (+3.2V)
34
CVSS
—
Ground terminal
35
BDR1
I
Serial data receive signal input terminal Not used (fixed at “H”)
36
BFSR1
I
Frame synchronization pulse signal input terminal Not used (fixed at “H”)
37
CVSS
—
Ground terminal
38
BCLKR1
O
Serial clock signal output to the CPU (IC801)
39
HCNTL0
I
Control signal input terminal Not used (fixed at “H”)
40
DVSS
—
Ground terminal
41, 42
BCLKR0, BCLKR2
I
Data receive clock input terminal Not used (fixed at “H”)
43, 44
BFSR0, BFSR2
I
Frame synchronization pulse signal input terminal Not used (fixed at “H”)
45
BDR0
I
Serial data receive signal input from the flash ROM (IC602)
46
HCNTL1
I
Control signal input terminal Not used (fixed at “H”)
47
BDR2
I
Serial data receive signal input from the EEPROM (IC603) and CPU (IC801)
48
BCLKX0
O
Serial clock signal output to the D/A converter (IC302)
49
BCLKX2
O
Serial clock signal output to the EEPROM (IC603) and CPU (IC801)
50
CVSS
—
Ground terminal
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