Sony NW-S4 Service Manual ▷ View online
NW-S4
14
14
3.4 Vp-p
22.7
µ
s
3.4 Vp-p
710 ns
4.1 Vp-p
3.5
µ
s
4.1 Vp-p
6.6
µ
s
3.2 Vp-p
125 ns
1.8 Vp-p
30.5
µ
s
1.2 Vp-p
59.1 ns
3.2 Vp-p
59.1 ns
3.4 Vp-p
22.7
µ
s
3.4 Vp-p
710 ns
3 Vp-p
20.8 ns
Note on Printed Wiring Board:
•
•
X
: parts extracted from the component side.
•
Y
: parts extracted from the conductor side.
•
f
: internal component.
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side:
Pattern face side:
Parts on the pattern face side seen from
(Conductor Side)
the pattern face are indicated.
Parts face side:
Parts on the parts face side seen from
(Component Side)
the parts face are indicated.
4-2.
NOTE FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS
• MAIN and SUB boards are multi-layer printed board.
However, the patterns of intermediate-layer have not been in-
cluded in this diagrams.
cluded in this diagrams.
Note on Schematic Diagram:
• All capacitors are in
• All capacitors are in
µ
F unless otherwise noted. pF:
µµ
F
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
specified.
•
%
: indicates tolerance.
•
f
: internal component.
•
C
: panel designation.
•
A
: B+ Line.
• Power voltage is dc 1.5 V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground in
playback mode.
no mark : PLAYBACK
no mark : PLAYBACK
∗
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Signal path.
F
: PLAYBACK
*
The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
form that of conventional IC.
cannot be measured, because its lead layout is different
form that of conventional IC.
• Waveforms
– MAIN Board –
– MAIN Board –
1
IC901
6
(XIN) (When power on)
50 mV/DIV, 50 ns/DIV
2
IC601
rk
(BCLKX0)
2 V/DIV, 500 ns/DIV
3
IC601
td
(BFSX0)
1 V/DIV, 5
µ
s/DIV
4
IC601
ua
(BCLKX1)
2 V/DIV, 50 ns/DIV
5
IC601
oj
(X2/CLKIN)
200 mV/DIV, 50 ns/DIV
6
IC801
2
(X1)
500 mV/DIV, 20
µ
s/DIV
7
IC801
5
(OSC2) (When power on)
100 mV/DIV, 200 ns/DIV
8
IC401
7
(LX)
1 V/DIV, 2
µ
s/DIV
9
IC404
9
(LX)
1 V/DIV, 2
µ
s/DIV
– SUB Board –
0
IC302
1
(LRCK)
1 V/DIV, 5
µ
s/DIV
qa
IC302
3
(SCLK)
2 V/DIV, 500 ns/DIV
qs
IC302
5
(MCLK)
2 V/DIV, 50 ns/DIV
3.2 Vp-p
59.1 ns
*
Lead Layouts (IC601 and IC901)
surface
Lead layout of conventional IC
CSP (chip size package)
NW-S4
15
15
D401
C-2
D402
B-2
D403
E-3
D405
B-3
D802
F-6
D901
E-4
D902
E-4
D903
F-6
IC401
B-2
IC402
A-2
IC403
A-2
IC404
B-4
IC405
E-2
IC601
F-10
IC602
B-9
IC603
G-8
IC604
E-8
IC801
B-6
IC802
F-6
IC901
E-7
Q401
B-3
Q402
E-3
Q403
B-3
Q405
F-7
Q801
C-2
Q901
E-6
CN901
USB
CONNECTOR
IC901
NOT
SUPPLIED
C421
C623
C424
C422
C427
C904
C902
C901
C813
C622
C621
C619
C615
C613
C609
C603
C614
C611
C606
C607
C610
C402
C417
C418
C406
C407
C408
C414
C410
C420
C601
C602
D403
D802
D903
IC604
IC603
(NOT SUPPLIED)
IC405
IC802
L402
L404
L403
Q405
Q402
Q901
VDR801
VDR802
VDR803
VDR804
R408
R409
R428
R430
R429
R436
R601
R602
R603
R607
R609
R610
R811
R812
R813
R814
R826
R827
R901
R902
R903
R904
R905
R906
R831
R604
R907
R908
R909
R910
R911
X901
D901
D902
L401
X601
IC601
NOT
SUPPLIED
THP401
C604
C818
C819
C416
C415
C413
C412
C411
C409
C423
C816
C903
C815
C812
C811
C804
C802
C620
C618
C608
C605
C801
D402
D405
IC401
IC404
IC402
IC403
IC801
Q403
Q401
VDR805
R410
R411
R412
R414
R415
R416
R420
R423
R424
R426
R435
R406
R404
R403
R402
R417
R418
R431
R419
R421
R612
R808
R809
R810
R815
R819
R820
R821
R822
R823
R824
R825
R830
R829
R605
R838
IC602
(NOT SUPPLIED)
X802
X801
D401
C821
R839
CN801
Q801
C404
R405
*
*
(11)
11
1-681-433-
MAIN BOARD
(CONDUCTOR SIDE)
DRY
BATTERY
SIZE “AA”
IEC DESIGNATION
R6
1PC. 1.5V
MAIN BOARD
(COMPONENT SIDE)
(11)
11
1-681-433-
A
SUB BOARD
CN802
1
4
E1
C2
C1
E2
B1 B2
A
B
C
D
E
F
G
1
2
3
4
5
6
7
8
9
10
11
4-3.
PRINTED WIRING BOARD – MAIN Board –
• Semiconductor
Location
Ref. No.
Location
(Page 18)
NW-S4
16
16
4-4.
SCHEMATIC DIAGRAM – MAIN Board (1/2) –
•
See page 14 for Waveforms.
•
See page 20 for IC Block Diagrams.
(Page 17)
NW-S4
17
17
4-5.
SCHEMATIC DIAGRAM – MAIN Board (2/2) –
•
See page 14 for Waveforms.
•
See page 20 for IC Block Diagrams.
(Page 16)
(Page 19)
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