Sony NW-E5 Service Manual ▷ View online
16
16
NW-E5
5-6. SCHEMATIC DIAGRAM – POWER SECTION –
IC B/D
IC B/D
IC B/D
IC B/D
z
Waveforms
1
VOLT/DIV : 1 V AC
TIME/DIV : 2
TIME/DIV : 2
µsec
3.6Vp-p
100kHz
z
See page 17 for Notes.
z
See page 18 for IC Block Diagrams
17
NW-E5
Note on Schematic Diagram:
• All capacitors are in
• All capacitors are in
µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω and
1
/
4
W or less unless otherwise
specified.
•
: B+ Line.
• Power voltage is dc 1.5 V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground in
playback mode.
no mark : PLAY
no mark : PLAY
∗
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 M
Ω).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
• Signal path.
J
: DIGITAL
F
: ANALOG
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
form that of conventional IC.
form that of conventional IC.
* Replacement of IC710 used in the set requires a spe-
cial tool.
18
NW-E5
• IC Block Diagrams –MAIN SECTION–
IC810 M66290AFP
IC751, 752, 753 TC5825FT
R / B
HIGH VOLTAGE
GENERATOR
ADDRESS REGISTER
COLUMN BUFFER
COLUMN DECORDER
DATA REGISTER
SENSE AMPLIFIER
MEMORY CELL
ARRAY
COMMAND REGISTER
STATUS REGISTER
LOW ADDRESS
BUFFER
LOW ADDRESS
DECORDER
I/O
CONTROL
ACTION
LOGIC
CONTROL
CONTROL
CIRCUIT
2
3
5
4
6
7
8
9
10
1
11
12
13
14
15
16
17
18
21
22
23
24
25
26
27
28
29
30
19
20
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC
NC
NC
NC
NC
XES
R/XB
XRE
XCE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
XWE
XWP
XEX-RST
NC
NC
NC
NC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
NC
NC
VCC
VCC
VSS
VSS
NC
NC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1
2
3
4
5
6
7
8
9
10
11
12
13
36
35
34
33
32
31
30
29
28
27
26
25
14 15 16
17 18 19 20 21 22
23 24
USB
TRANSCEIVER
SERIAL
INTERFACE
ENGINE
USB
PERIPHERAL
CIRCUIT
CLOCK
CONTROL
(OSCILLATOR/
PLL)
TCK
XTRST
TEST1
TR_ON
VBUS
GND
VCC
D+
TMS
TDI
TDO
GND
XIN
XOUT
VCC
A1
A2
A3
A4
A5
A6
D0
D1
D0
D1
48 47 46 45 44 43 42 41
40 39 38 37
XRST
DREQ
DACK
XCS
XWR
XRD
XINT
TEST2
D15
D14
D13
D12
DREQ
DACK
CS
WR
RD
INT
D15
D14
D13
D12
D –
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
VCC
GND
DACK
DREQ
CS
WR
RD
INT
DEVICE
CONTROL
UNIT
END POINT
BUFFER
(3k BYTE FIFO)
CPU
REGISTER
1
XOE
2
1Q
3
1D
4
2D
5
2Q
6
3Q
7
3D
8
4D
9
4Q
10
GND
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
1D
C1
C2
2D
3D
C3
C4
4D
8D
C8
C7
7D
6D
C6
C5
5D
IC853 SN74LVC374APWR
19
NW-E5
IC302 TA2131FL (EL)
IC301 AK4352VT-E2
• IC Block Diagrams –POWER SECTION–
SERIAL
INPUT
INTERFACE
CLOCK DIVIDER
15 VCML
14 AOUTL
13
11
LPF
12
10 VDD
VREF
VCMR
AOUTR
9
VSS
CKS
16
2
3
4
6
5
7
8
XPD
BLCK
DEM
DIF1
DIF0
SDATA
LRCK
MCLK 1
LPF
∆ Σ
MODULATOR
∆ Σ
MODULATOR
8X
INTERPOLATOR
8X
INTERPOLATOR
DE-EMPHASIS
CONTROL
V REF
MT
SW
BST
SW
BEEP
19
20
21
22
23
24
18
17
16
15
14
13
PW
SW
SW
12
11
10
8
7
BST1
9
BST2
6
5
4
3
2
1
BST
AGC
PW
B
PW
A
ADD
TC MT
VCC1
INB
INA
BEEP
OUTB
BEEP
OUTA
VCC2
OUTA
PWR
GND
OUTB
DET
AGC IN
BST OUT
BST NF2
LPF2
BST NF1
LPF1
VREF
VREF IN
GND
BEEP IN
BST SW
MUTE
PWSW
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