Sony NW-A1000 Service Manual ▷ View online
41
NW-A1000
Pin No.
Pin Name
I/O
Description
61
PAD_GND
-
Ground terminal (for I/O)
62
SCLK1
I
Bit clock signal input from the PLD
63
LRCK1
I
L/R sampling clock signal input from the PLD
64
SDATAO1
O
Audio data output to the PLD
65
TSB_XLT
O
TSB latch signal output terminal Not used
66
TSB_RW
O
TSB read/write control signal output to the PLD
67
LCD_DC
O
Resister selection signal output to the EL module
68
FS256
O
11.2896 MHz clock signal output to the D/A converter and PLD
69
SDATAI3
I
Audio data input from the PLD
70, 71
AD_KEY2,
AD_KEY1
I
Set key input terminal (A/D input)
72
AD_RMCKEY (K1)
I
External key input terminal (A/D input)
73
ADVDD
-
Power supply terminal (+3V) (for A/D converter)
74
AD_GND
-
Ground terminal (for A/D converter)
75
AD_BATT
I
Battery voltage monitor input from the power control
76
AD_CRADLE
I
Cradle detection signal input terminal
77
AD_GSEN_XYZ
I
G-sensor input terminal
78
ADREF
-
Reference voltage terminal (for A/D converter)
79
ADOUT
-
Reference voltage terminal (for A/D converter)
80
LRCK3
I
L/R sampling clock signal input from the PLD
81
SCLK3
I
Bit clock signal input from the PLD
82
RDY_XBUSY
I
Ready/busy selection signal input from the NOR flash memory "L": busy, "H": ready
83
XBATT_DET
I
Battery insert detection signal input terminal Not used
84
XINT_DENDE
I
Interrupt request signal input from the PLD
85
USB _IF_EN
O
USB interface enable signal output terminal Not used
86
XINT_USB
I
Interrupt request signal input from the USB controller
87
XINT_HDD
I
Interrupt request signal input from the hard disk drive Not used
88
GSEN_SEL2
O
G-sensor axis selection signal output terminal
89
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
90
CORE_GND
-
Ground terminal (for core)
91
N/C
I
Not used
92
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
93
TCXD0
O
RS232C output terminal for external monitor Not used
94
RXD0
I
RS232C input terminal for external monitor Not used
95
HOLD_KEY
I
HOLD key input terminal
96
MSINS
I
Memory stick insert detection signal input terminal Not used
97
PAD_GND
-
Ground terminal (for I/O)
98
DENDE_SS
I
Interrupt permission signal input from the PLD
99
XRESET_USB
O
Reset signal output to the USB controller "L": reset
100
PSTCLK
O
PSTCLK output terminal Not used
101
DSO
O
DSO output terminal Not used
102
DSI
I
DSI input terminal Not used
103
(N/U)
I
Not used
104
BKPT
I
BKPT input terminal
105
DSCLK
I
DSCLK input terminal Not used
106
RSTI
I
Reset signal input from the power control "L": reset
107
SCLK2
O
Bit clock signal output to the D/A converter
108
LRCK2
O
L/R sampling clock signal output to the D/A converter
42
NW-A1000
Pin No.
Pin Name
I/O
Description
109
LINOUT
O
Not used
110
LININ
I
Not used
111
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
112
SDATAO2
O
Audio data output to the D/A converter
113
NC
I
Not used
114
Hi-Z
-
Not used
115 to 117 TEST0 to TEST2
I
Input terminal for the test mode setting
118
SDW
O
Write enable signal output to the SD-RAM
119
SDCAS
O
Column address signal output to the SD-RAM
120
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
121
SDRAS
O
Row address signal output to the SD-RAM
122
SDCS0
O
Chip select signal output to the SD-RAM
123
SDLDQ
O
Write mask signal output to the SD-RAM (lower byte)
124
SDUDQ
O
Write mask signal output to the SD-RAM (upper byte)
125
BCLKE
O
Clock enable signal output to the SD-RAM
126
BCLK
O
Clock signal output to the SD-RAM
127, 128
DATA31, DATA30
I/O
Two-way data bus with the USB controller, SD-RAM, NOR flash memory and PLD
129
PAD_GND
-
Ground terminal (for I/O)
130 to 134
DATA29 to DATA25
I/O
Two-way data bus with the USB controller, SD-RAM, NOR flash memory and PLD
135
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
136
DATA24
I/O
Two-way data bus with the USB controller, SD-RAM, NOR flash memory and PLD
137 to 140
DATA23 to DATA20
I/O
Two-way data bus with the SD-RAM and NOR flash memory
141
PAD_GND
-
Ground terminal (for I/O)
142 to 144
DATA19 to DATA17
I/O
Two-way data bus with the SD-RAM and NOR flash memory
145 to 163
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
164 to 189
PAD_GND
-
Ground terminal (for I/O)
190 to 192
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
193
BGA_NC_A1
-
Not used
194
BGA_NC_A14
-
Not used
195
BGA_NC_P1
-
Not used
196
BGA_NC_P14
-
Not used
43
NW-A1000
IC8001 LC4128ZC-75MN132C-U5 (PLD)
Pin No.
Pin Name
I/O
Description
1
GND
-
Ground terminal
2
TDI
I
Data input terminal (for JTAG) Not used
3
VCCIO0
-
Power supply terminal (+3V) (for I/O)
4
EX_MULTI_SCK
O
Serial data transfer clock signal output to the real time clock and power control
5
CRADLE_SCK
O
Serial data transfer clock signal output to the cradle
6
FRES_D28
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
7
CRADLE_SI
O
Serial data output to the cradle
8
MULTI_SI
O
Serial data output to the main system controller
9
FRES_D29
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
10
GNDIO0
-
Ground terminal (for I/O)
11
EX_MULTI_SO
O
Serial data output to the D/A converter, power control and EL module
12
LCD_XCS
O
Chip select signal output to the EL module "L" active
13
SCLK1
O
Bit clock signal output to the main system controller
14
CRADLE_CS
O
Chip select signal output to the cradle "H" active
15
LRCK1
O
L/R sampling clock signal output to the main system controller
16
TSB
I/O
Two-way TSB communication data bus with the remote commander
17
VCCIO0
-
Power supply terminal (+3V) (for I/O)
18
DAC_XCS
O
Chip select signal output to the D/A converter "L" active
19
FRES_D30
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
20
RTC_CE
O
Chip enable signal output to the real time clock "H" active
21
FRES_D31
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
22
PWR_STRB
O
Chip select signal output to the power control "H" active
23
PWR_SLEEP
O
Standby signal output to the power control "H": standby mode
24
GNDIO0
-
Ground terminal (for I/O)
25
PWR_FFCLR
O
Start factor clear signal output to the power control "H" active
26
BAT_MON_CTL
O
Battery voltage monitor on/off control signal output to the power control
"H": battery voltage monitor on
"H": battery voltage monitor on
27
VBUS_LIM
O
USB current limit control signal output to the power control
"L": 100 mA, "H": 500 mA
"L": 100 mA, "H": 500 mA
28
GPIO8
I/O
Not used
29
GPIO20
O
Not used
30
GPIO9
I/O
Not used
31
VCCIO0
-
Power supply terminal (+3V) (for I/O)
32
TCK
I
Clock signal input terminal (for JTAG) Not used
33
VCC
-
Power supply terminal (+1.8V) (for core)
34
GND
-
Ground terminal
35
KEY_LED2
O
LED drive signal output for key illumination "H": LED on
36
XHDD_PWR_CTL
O
Power on/off control signal output for hard disk drive unit "L": power on
37
XUSLEEP
O
Sleep signal output to the USB controller "L": sleep mode
38
HP_MUTE
O
Muting on/off control signal output to the audio amplifier "H": muting on
39
IIS_CLR
O
IIS CLR control signal output terminal
40
EL_PWR
O
Power on/off control signal output for EL module "H": power on
41
GNDIO0
-
Ground terminal (for I/O)
44
NW-A1000
Pin No.
Pin Name
I/O
Description
42
VCCIO0
-
Power supply terminal (+3V) (for I/O)
43
CRD_MUTE1
O
Headphone/cradle selection signal output for audio output "L": headphone, "H": cradle
44
RESET_TSB
O
TSB reset signal output terminal Not used
45
HP_LINE_SEL
O
Headphone/cradle selection signal output for audio output to the audio amplifier
"L": cradle, "H": headphone
"L": cradle, "H": headphone
46
XGSEN_PWR_CTL
O
Standby signal output to the G-sensor "L": standby mode
47
KEY_LED1
O
LED drive signal output for key illumination "H": LED on
48
D33_MODE
O
+3.3V regulator on/off control signal output terminal Not used
49
LCD_SO
I
Serial data input from the EL module Not used
50
NC
-
Not used
51
VCC
-
Power supply terminal (+1.8V) (for core)
52
NC
-
Not used
53
DC_OUT_CTL
O
Power on/off control signal output for cradle "H": power on
54
AF_DCIN_DET
I
AC adaptor connection detection signal input from the power control
"L": AC adaptor is connected
"L": AC adaptor is connected
55
SPI_CS2
I
Chip select signal input for serial control from the main system controller
56
SUSPEND
O
Power on/off control signal output at suspend mode "H": power on
57
SPI_CS1
I
Chip select signal input for serial control from the main system controller
58
JACK_DET
I
Cradle jack detection signal input terminal "L": cradle jack is detected
59
VCCIO1
-
Power supply terminal (+3V) (for I/O)
60
GNDIO1
-
Ground terminal (for I/O)
61
XCHG_STAT1
I
Charge state signal input terminal
62
GPIO5
I
Not used
63
XCHG_STAT2
I
Charge state signal input from the power control
64
SPI_CS0
I
Chip select signal input for serial control from the main system controller
65
DEN_SCK0
O
Serial data transfer clock signal output to the sub system controller
66
PLD_BEEP
O
Beep signal output to the audio amplifier
67
GND
-
Ground terminal
68
TMS
I
Mode selection signal input terminal (for JTAG)
69
VCCIO1
-
Power supply terminal (+3V) (for I/O)
70
MILTI_SCK
I
Serial data transfer clock signal input from the main system controller
71
CRADLE_SO
I
Serial data input from the cradle
72
TSB_SO
I
TSB serial data input from the main system controller
73
DEN_SO0
I
Serial data input from the sub system controller
74
TSB_RW
I
TSB read/write control signal input from the main system controller
75
NC
-
Not used
76
GNDIO1
-
Ground terminal (for I/O)
77
ADP_DET
I
AC adaptor/USB identification signal input terminal "L": USB, "H": AC adaptor
78
DEN_LRCKI
O
L/R sampling clock signal output to the sub system controller
79
NC
-
Not used
80
DEN_BCKI
O
Bit clock signal output to the sub system controller
81, 82
NC
-
Not used
83
VCCIO1
-
Power supply terminal (+3V) (for I/O)
84
SCLK2
I
Bit clock signal input from the main system controller
85
XRST
I
Reset signal input from the power control "L": reset
86
DEN_XRDE
I
Ready/busy selection signal input from the sub system controller "L": ready, "H": busy
87
DENDE_SERQ
I
Interrupt request signal input from the main system controller
88
WAKEUP_DENDE
I
Wake-up signal input from the main system controller
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