Sony NW-A1000 Service Manual ▷ View online
37
NW-A1000
Pin No.
Pin Name
I/O
Description
50, 51
TEST6, TEST5
O
Output terminal for the test
52 to 55
TEST4 to TEST1
I
Input terminal for the test
56
DVDD3
-
Power supply terminal (+1.3V)
57
DVSS1
-
Ground terminal
58
TEST0
I
Input terminal for the test
59
TCK
I
Clock signal input terminal (for JTAG) Not used
60
TDI
I
Data input terminal (for JTAG) Not used
61
VDIO3
-
Power supply terminal (+1.8V) (for I/O)
62
TMS
I
Mode selection signal input terminal (for JTAG) Not used
63
TDO
O
Data output terminal (for JTAG) Not used
64
NTRST
I
Reset signal input terminal (for JTAG) Not used
38
NW-A1000
IC5001 S1R72003BOOA100 (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
R1
I/O
Internal operation setting terminal
2
N.C.
-
Not used
3
AVSS
-
Ground terminal (analog system)
4
AVDD
-
Power supply terminal (+3.3V) (analog system)
5
AVSS
-
Ground terminal (analog system)
6
AVDD
-
Power supply terminal (+3.3V) (analog system)
7
AVSS
-
Ground terminal (analog system)
8
DP
I/O
USB data (+) input/output terminal
9
AVSS
-
Ground terminal (analog system)
10
DM
I/O
USB data (-) input/output terminal
11
AVSS
-
Ground terminal (analog system)
12
AVDD
-
Power supply terminal (+3.3V) (analog system)
13
TSTEN
I
Input terminal for the test mode setting
14
VBUS
I
USB bus detection signal input terminal
15
XRESET
I
Reset signal input from the power control "L": reset
16
XSLEEP
I
Sleep signal input from the PLD "L": sleep mode
17 to 24
CA0 to CA7
I
Address signal input from the main system controller
25
VSS
-
Ground terminal (logic system)
26
VDD
-
Power supply terminal (+3.3V) (logic system)
27
XCS
I
Chip select signal input terminal Not used
28
XRD
I
Read signal input from the main system controller
29
XWAIT
O
Wait signal output to the main system controller
30
XWR
I
Write signal input from the main system controller
31
XINT
O
Interrupt request signal output to the main system controller
32 to 35
CD0 to CD3
I/O
Two-way data bus with the main system controller, SD-RAM, NOR flash memory and PLD
36
VSS
-
Ground terminal (logic system)
37 to 40
CD4 to CD7
I/O
Two-way data bus with the main system controller, SD-RAM, NOR flash memory and PLD
41
VDD
-
Power supply terminal (+3.3V) (logic system)
42
ATPGEN
I
Input terminal for the test mode setting
43
SCANEN
I
Input terminal for the test mode setting
44, 45
TPORT0, TPORT1
I/O
Input/output terminal for the test mode setting
46, 47
TIN0, TIN1
I
Input terminal for the test mode setting
48
VSS
-
Ground terminal (logic system)
49
OSCOUT
O
Clock signal output terminal Not used
50
VSS
-
Ground terminal (logic system)
51
VDD
-
Power supply terminal (+3.3V) (logic system)
52
XHRESET
O
Reset signal output to the hard disk drive unit "L": reset
53 to 60
HDD4 to HDD11
I/O
Two-way data bus with the hard disk drive unit
61
VSS
-
Ground terminal (logic system)
62 to 69
HDD0 to HDD3,
HDD12 to HDD15
I/O
Two-way data bus with the hard disk drive unit
70
VDD
-
Power supply terminal (+3.3V) (logic system)
71
HDMARQ
I
DMA request signal input from the hard disk drive unit
72
XHIOW
O
Write signal output to the hard disk drive unit
73
XHIOR
O
Read signal output to the hard disk drive unit
39
NW-A1000
Pin No.
Pin Name
I/O
Description
74
HIORDY
I
Wait signal input from the hard disk drive unit
75
VSS
-
Ground terminal (logic system)
76
VDD
-
Power supply terminal (+3.3V) (logic system)
77
XHDMACK
O
DMA acknowledge signal output to the hard disk drive unit
78
HINTRQ
I
Interrupt request signal input from the hard disk drive unit
79
HA1
O
Address signal output to the hard disk drive unit
80
XHPDIAG
I
Diagnosis sequence compression signal input from the hard disk drive unit
81, 82
HA0, HA2
O
Address signal output to the hard disk drive unit
83, 84
HCS0, HCS1
O
Chip select signal output to the hard disk drive unit
85
XHDASP
I
Drive valid signal and slave drive detection signal input from the hard disk drive unit
86
VSS
-
Ground terminal (logic system)
87, 88
CLKSEL0,
CLKSEL1
I
Input terminal for oscillation frequency setting Fixed at 12 MHz in this set
89
VSS
-
Ground terminal (logic system)
90
XVSS
-
Ground terminal (logic system)
91
XVDD
-
Power supply terminal (+3.3V) (logic system)
92
VDD
-
Power supply terminal (+3.3V) (logic system)
93
PVDD
-
Power supply terminal (+3.3V) (for PLL)
94
VDD
-
Power supply terminal (+3.3V) (logic system)
95
PVSS
-
Ground terminal (for PLL)
96 to 98
NC
-
Not used
99
XI
I
Sub system clock input terminal (12 MHz)
100
XO
O
Sub system clock output terminal (12 MHz)
40
NW-A1000
IC6005 SCF5250 (MAIN SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DATA16
I/O
Two-way data bus with the SD-RAM and NOR flash memory
2
A23
O
Address signal output to the SD-RAM
3
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
4
A22
O
Address signal output to the SD-RAM
5 to 8
A21 to A18
O
Address signal output to the SD-RAM and NOR flash memory
9
PAD_GND
-
Ground terminal (for I/O)
10
A17
O
Address signal output to the NOR flash memory
11 to 14
A16 to A13
O
Address signal output to the SD-RAM and NOR flash memory
15
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
16, 17
A12, A11
O
Address signal output to the SD-RAM and NOR flash memory
18
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
19
CORE_GND
-
Ground terminal (for core)
20, 21
A10, A9
O
Address signal output to the SD-RAM and NOR flash memory
22 to 25
A8 to A5
O
Address signal output to the USB controller and NOR flash memory
26
PAD_GND
-
Ground terminal (for I/O)
27
A4
O
Address signal output to the USB controller and NOR flash memory
28 to 30
A3 to A1
O
Address signal output to the USB controller, NOR flash memory and PLD
31
CS0
O
Chip select signal output to the NOR flash memory
32
XRW
O
Read/write control signal output to the NOR flash memory, PLD and EL module
33
OSC_PAD_VDD
-
Power supply terminal (+3V) (for OSC)
34
CRIN
I
Main system clock input terminal (22.5792 MHz)
35
CROUT
O
Main system clock output terminal (22.5792 MHz)
36
OSC_PAD_GND
-
Ground terminal (for OSC)
37
PLL_CORE1_VDD
-
Power supply terminal (+1.1V) (for PLL)
38
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
39
CORE_GND
-
Ground terminal (for core)
40
PLL_CORE1_GND
-
Ground terminal (for PLL)
41
OE
O
Read signal output to the NOR flash memory, PLD and EL module
42
IDE_DIOW
O
Write signal output to the USB controller
43
IDE_IOPDY
I
Wait signal input from the USB controller
44
IDE_DIOR
O
Read signal output to the USB controller
45
BUFFENB2
O
BUFFENB signal output terminal Not used
46
GSEN_SEL1
O
G-sensor axis selection signal output terminal
47
TA
I
Access complete signal input terminal Not used
48
WAKEUP
I
Wake-up signal input from the USB controller
49
XRESET_LCD
O
Reset signal output to the EL module "L": reset
50
SPI_CS2
O
Chip select signal output for serial control to the PLD
51
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
52
WAKEUP_DENDE
O
Wake-up signal output to the PLD
53
DENDE_SREQ
O
Request signal output to the PLD
54
DATA_READY
I
Ready signal input from the PLD
55
CS1
O
Chip select signal output to the PLD
56
MULTI_SI
I
Serial data input from the PLD and power control
57
MULTI_SCK
O
Serial data transfer clock signal output to the PLD
58
MULTI_SO
O
Serial data output to the real time clock and PLD
59, 60
SPI_CS1, SPI_CS0
O
Chip select signal output for serial control to the PLD
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